CY14B101J - Cypress Semiconductor

CY14B101J 1-Mbit (128 K X 8) Serial (I2C) nvSRAM

Clock. Runs at speeds up to a maximum of fSCL. I/O. Input/Output of data through I2C interface. Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be left open if not connected. Slave Address. Defines the slave address for I2C. This pin is internally pulled LOW and hence can be left open if not connected. Hard.

Features

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■ CY14C101J CY14B101J, CY14E101J 2 1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor (except for CY14X101J1) High reliability
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❐ Industry standard configurations
❐ Operating voltages:
• CY14C101J: VCC = 2.4 V to 2.6 V
• CY14B101J: VCC = 2..