Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE1 and OE0) are provided to simplify cascading and .
• Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
•
Typical Propagation Delay of 13ns 15pF, TA = 25oC (CD74HC237)
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CD74HC132 |
Texas Instruments |
High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger | |
2 | CD74HC138 |
Texas Instruments |
High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer Inverting/Noninverting | |
3 | CD74HC138-Q1 |
Texas Instruments |
3- TO 8-LINE INVERTING DECODER/DEMULTIPLEXER | |
4 | CD74HC138E |
Texas Instruments |
High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer Inverting/Noninverting | |
5 | CD74HC138M |
Texas Instruments |
High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer Inverting/Noninverting | |
6 | CD74HC139 |
Texas Instruments |
Dual 2- to 4-Line Decoder/Demultiplexer | |
7 | CD74HC10 |
Texas Instruments |
Triple 3-Input NAND Gates | |
8 | CD74HC107 |
Texas Instruments |
Dual J-K Flip-Flop | |
9 | CD74HC109 |
Texas Instruments |
Dual J-K Flip-Flop | |
10 | CD74HC10E |
Texas Instruments |
Triple 3-Input NAND Gates | |
11 | CD74HC10M |
Texas Instruments |
Triple 3-Input NAND Gates | |
12 | CD74HC11 |
Texas Instruments |
Triple 3-Input AND Gate |