This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT10M SOIC (14) 8.70 mm × 3.90 mm CD74HCT10E PDIP (14) 19.30 mm × 6.40 mm CD54HCT10F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see .
• LSTTL input logic compatible
– VIL(max) = 0.8 V, VIH(min) = 2 V
• CMOS input logic compatible
– II ≤ 1 µA at VOL, VOH
• Buffered inputs
• 4.5 V to 5.5 V operation
• Wide operating temperature range:
-55°C to +125°C
• Supports fanout up to 10 LSTTL loads
• Significant power reduction compared to LSTTL
logic ICs
2 Applications
• Alarm / tamper detect circuit
• S-R latch
3 Description
This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y = A
● B
● C in positive logic.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD74HCT10M
SOIC.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CD54HCT10 |
Texas Instruments |
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2 | CD54HCT109 |
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3 | CD54HCT11 |
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4 | CD54HCT112 |
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5 | CD54HCT123 |
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7 | CD54HCT126 |
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8 | CD54HCT132 |
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9 | CD54HCT132J |
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Quadruple 2-Input NAND Gates | |
10 | CD54HCT138 |
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11 | CD54HCT138F |
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High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer Inverting/Noninverting | |
12 | CD54HCT139 |
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Dual 2- to 4-Line Decoder/Demultiplexer |