CD4015BC - National Semiconductor

CD4015BC Dual 4-Bit Static Shift Register

The CD4015BM CD4015BC contains two identical 4-stage serial-input parallel-output registers with independent ‘‘Data’’ ‘‘Clock ’’ and ‘‘Reset’’ inputs The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition A logic high on the ‘‘Reset’’ input resets all four stages covered by that i.

Features

Y Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Medium speed operation Fully static design 3 0V to 18V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS 8 MHz (typ ) clock rate VDD b VSS e 10V Applications Y Y Y Serial-input parallel-output data queueing Serial to parallel data conversion General purpose register Connection Diagram and Truth Table Dual-In-Line Package TL F 5948
  – 1 CL U L L K X D 0 1 X X R 0 0 0 1 Q1 0 1 Q1 0 Qn Qnb1 Qnb1 Qn 0 (No change) U Level change X e Don’t care case Order Number CD4015B C1996 National Semicon.