Symbol CLK Type Input CKE Input A11 A0-A10 Input Input CS# Input RAS# Input CAS# Input WE# Input LDQM, UDQM Input AS4C1M16S-C&I Table 3. Pin Details Description Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output regi.
Fast access time: 5.4/5.4ns
Fast clock rate: 166/143 MHz
Self refresh mode: standard
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Industrial Temperature: -40~85°C
JEDEC standard +3.3V0.3V power supply
Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C)
Inte.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | AS4C1M16S-I |
Alliance Memory |
1M x 16 bit Synchronous DRAM | |
2 | AS4C1M16S |
Alliance Memory |
1M x 16 bit Synchronous DRAM | |
3 | AS4C1M16E5 |
Alliance Semiconductor |
5V 1M x 16 CMOS DRAM | |
4 | AS4C1M16F5 |
Alliance Semiconductor |
5V 1M x 16 CMOS DRAM | |
5 | AS4C1024 |
Austin Semiconductor |
1M x 1 DRAM | |
6 | AS4C1259 |
Austin Semiconductor |
256K x 1 DRAM | |
7 | AS4C1259883C |
Austin Semiconductor |
256K x 1 DRAM | |
8 | AS4C128M16D2A-25BCN |
Alliance Semiconductor |
2Gb DDR2 | |
9 | AS4C128M16D2A-25BIN |
Alliance Semiconductor |
2Gb DDR2 | |
10 | AS4C128M16D3A-12BIN |
Alliance Semiconductor |
2Gb Double-Data-Rate-3 DRAM | |
11 | AS4C128M16D3B-12BCN |
Alliance Semiconductor |
Double-data-rate architecture | |
12 | AS4C128M16D3LA-12BIN |
Alliance Semiconductor |
128M x 16 bit DDR3L Synchronous DRAM |