AP2302 - BCD Semiconductor

AP2302 3A DDR TERMINATION REGULATOR

The AP2302 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 3A current continuously, offers enough current for most DDR applications. Output voltage is designed to track the reference voltage within a 2% (DDR I) and 3% (DDR II) tolerance for load regulation wh.

Features

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· Support Both DDR I (1.25VTT) and DDR II (0.9VTT) Requirements Source and Sink Current up to 3A High Accuracy Output Voltage at Full-load Adjustable VOUT by External Resistors Shutdown for Standby or Suspend Operation with High-impedance Output Mode Applications
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· DDR-SDRAM Termination DDR-II Termination SSTL-2 Termination SOIC-8 TO-252-5L TO-263-5L Figure 1. Package Types of AP2302 Jul. 2006 Rev. 1. 2 1 BCD Semiconductor Manufacturing Limited Preliminary Datasheet 3A DDR TERMINATION REGULATOR Pin Configuration M Package (SOIC-8) VIN GND REFEN VOUT 1 2 3 4 8 7 6 5 VCNTL VC.