A2S56D20CTP is a 4-bank x 16,777,216-word x 4-bit, A2S56D30CTP is a 4-bank x 8,388,608-word x 8bit, A2S56D40CTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strob , and output data and d.
- Vdd=Vddq=2.5V ± 0.2V power supply for -6,-75. -Vdd=Vddq=2.6V ± 0.1V power supply for -5. - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strob (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5/ 3 (programmable) ; Burst length - 2 / 4 / 8 (programmable) Burst type - .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | A2S56D20CTP |
Powerchip Semiconductor |
256Mb DDR SDRAM | |
2 | A2S56D30CTP |
Powerchip Semiconductor |
256Mb DDR SDRAM | |
3 | A2SHB |
SLS SEMICONDUCTOR |
N-Channel MOSFET | |
4 | A2SHB |
Low Power Semi |
N-Channel MOSFET | |
5 | A2SHB |
HAOHAI |
N-Channel MOSFET | |
6 | A2SHB |
YUSHIN |
SOT-23 FET | |
7 | A2SI |
Zentrum Mikroelektronik Dresden |
Release Notes IC Revision C | |
8 | A2SI-E |
Zentrum Mikroelektronik Dresden |
Advanced AS-Interface IC | |
9 | A2SI-L |
Zentrum Mikroelektronik Dresden |
Low End Device AS-Interface IC | |
10 | A20 |
Allwinner Technology |
Processor | |
11 | A200-D90 |
NISSEI |
brake of motor / BRAKE PACK / (A100-D45) | |
12 | A2002 |
HR |
2.00mm Pitch Wire to Board Connector |