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The 9DBV0231 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Recommended Application 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 2 – 1-200MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF .
• 2
– 1-200MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms (12k-20MHz)
Block Diagram
Features/Benefits
• LP-HCSL outputs; save 4 resistors compared to standard
HCSL outputs
• 35mW typical power consumption in PLL mode; reduced
thermal concerns
• Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
.
9DBV0231 - Renesas
The 9DBV0231 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock ma.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | 9DBV0241 |
IDT |
2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer |
|
| 2 | 9DBV0431 |
IDT |
4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer |
|
| 3 | 9DBV0431 |
Renesas |
Zero-delay/Fanout Buffer |
|
| 4 | 9DBV0441 |
IDT |
4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB |
|
| 5 | 9DBV0441 |
Renesas |
1.8V PCIe Gen1-4 ZDB/FOB |
|
| 6 | 9DBV0531 |
IDT |
5-output 1.8V HCSL Fanout Buffer |
|
| 7 | 9DBV0531 |
Renesas |
5 to 9-Output 1.8V Low-Power Buffers |
|
| 8 | 9DBV0541 |
IDT |
5 Output 1.8V HCSL Fanout Buffer |
|
| 9 | 9DBV0541 |
Renesas |
5 to 9-Output 1.8V Low-Power Buffers |
|
| 10 | 9DBV0631 |
IDT |
6-output 1.8V PCIe Gen1-2-3 ZDB/FOB |
|
| 11 | 9DBV0631 |
Renesas |
6-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer |
|
| 12 | 9DBV0641 |
IDT |
Clock Buffer |
|