. . . 10 Block diagram 11 Product overview . . . . . . 12 4.1 Central processing unit STM8.
Core
• 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
• Extended instruction set
Memories
• Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles
• RAM: 1 Kbyte
• Data memory: 128 bytes true data EEPROM;
endurance up to 100 k write/erase cycles
Clock, reset and supply management
• 2.95 V to 5.5 V operating voltage
• Flexible clock control, 4 master clock sources
– Low-power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
• Clock security system with clock monito.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 8S003F3P6 |
STMicroelectronics |
8-bit MCU | |
2 | 8S003K3 |
STMicroelectronics |
STM8S003K3 | |
3 | 8S2TH02I |
Thinki Semiconductor |
16.0 Ampere Ceramic Insulated Dual Series Connection Ultra Fast Recovery Rectifiers | |
4 | 8S2TH04I |
Thinki Semiconductor |
16.0 Ampere Ceramic Insulated Dual Series Connection Ultra Fast Recovery Rectifiers | |
5 | 8S2TH06I |
Thinki Semiconductor |
16.0 Ampere Ceramic Insulated Dual Series Connection Ultra Fast Recovery Rectifiers | |
6 | 8S650GXM |
GIGABYTE |
Motherboard Manual | |
7 | 8S89296 |
Renesas |
LVDS Programmable Delay Line | |
8 | 8S89831I |
IDT |
Differential LVPECL-To-LVPECL/ECL Fanout Buffer | |
9 | 8S89831I |
Renesas |
Differential LVPECL-To-LVPECL/ECL Fanout Buffer | |
10 | 8S89832I |
Renesas |
1-to-4 Differential-to-LVDS Fanout Buffer | |
11 | 8S89832I |
IDT |
1-to-4 Differential-to-LVDS Fanout Buffer | |
12 | 8S89833 |
IDT |
1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination |