This Schottky memory is organized in the popular 512 words by 8 bits configuration A memory enable input is provided to control the output states When the device is enabled the outputs represent the contents of the selected word When disabled the 8 outputs go to the ‘‘OFF’’ or high impedance state www.DataSheet4U.com PROMs are shipped from the factory with l.
Y Y
Y Y
Y Y
Advanced titanium-tungsten (Ti-W) fuses Schottky-clamped for high speed Address access 45 ns max Enable access 30 ns max Enable recovery 30 ns max PNP inputs for reduced input loading All DC and AC parameters guaranteed over temperature Low voltage TRI-SAFETM programming Open-collector outputs
Block Diagram
TL D 9715
– 1
Pin Names A0
–A8 G GND Q0
–Q7 VCC Addresses Output Enable Ground Outputs Power Supply
TRI-SAFETM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation
TL D 9715
RRD-B30M105 Printed in U S A
Connection Diagrams
Dual-In.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74S405N |
Unitra Cemi |
Dekoder binarny | |
2 | 74S00 |
ETC |
QUAD 2-input NAND GATE | |
3 | 74S04 |
National Semiconductor |
HEX INVERTING GATES | |
4 | 74S04 |
Texas Instruments |
Hex Inverters | |
5 | 74S08 |
Fairchild Semiconductor |
Quad 2-Input AND Gate | |
6 | 74S08 |
National Semiconductor |
Quad 2-Input AND Gates | |
7 | 74S08 |
Texas Instruments |
Quadruple 2-Input Positive-AND Gates | |
8 | 74S08N |
Fairchild Semiconductor |
Quad 2-Input AND Gate | |
9 | 74S10 |
TW |
STTL type three 3-input NAND gate | |
10 | 74S112 |
Fairchild Semiconductor |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | |
11 | 74S133 |
SYC |
13-Input NAND Gate | |
12 | 74S134 |
Fairchild |
12-INPUT POSITIVE-NAND GATES |