Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs are provided for each of the two four-line sections. Features s Permits multiplexing from N lines to 1 line s Performs parallel-to-serial conversion s Strobe (enabl.
s Permits multiplexing from N lines to 1 line s Performs parallel-to-serial conversion s Strobe (enable) line provided for cascading (N lines to n lines) s High fan-out, low-impedance, totem-pole outputs s Typical average propagation delay times From data 6 ns From strobe 9.5 ns From select 12 ns s Typical power dissipation 225 mW Ordering Code: Order Number Package Number Package Description DM74S153N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Select Inputs Data Inputs Strobe B A C0 C1 C2 C3 G XX X X X X H LL L .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74S15 |
TW |
STTL type three 3-input AND gate | |
2 | 74S157 |
Fairchild Semiconductor |
Quad 1 of 2 Line Data Selectors/Multiplexers | |
3 | 74S158 |
Fairchild Semiconductor |
Quad 1 of 2 Line Data Selectors/Multiplexers | |
4 | 74S10 |
TW |
STTL type three 3-input NAND gate | |
5 | 74S112 |
Fairchild Semiconductor |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | |
6 | 74S133 |
SYC |
13-Input NAND Gate | |
7 | 74S134 |
Fairchild |
12-INPUT POSITIVE-NAND GATES | |
8 | 74S134 |
Signetics |
12-INPUT POSITIVE-NAND GATES | |
9 | 74S135 |
Fairchild |
Quad Exclusive OR/NOR Gate | |
10 | 74S135 |
Signetics |
Quad Exclusive OR/NOR Gate | |
11 | 74S138 |
Fairchild Semiconductor |
Decoder/Demultiplexer | |
12 | 74S139 |
Fairchild Semiconductor |
Decoder/Demultiplexer |