The 74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device whe.
I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C I I I I I I I I NXP Semicon.
The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and re.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LVC2G74-Q100 |
nexperia |
Single D-type flip-flop | |
2 | 74LVC2G00 |
Diodes |
DUAL 2-INPUT NAND GATE | |
3 | 74LVC2G00 |
NXP |
Dual 2-input NAND gate | |
4 | 74LVC2G00 |
nexperia |
Dual 2-input NAND gate | |
5 | 74LVC2G00-Q100 |
NXP |
Dual 2-input NAND gate | |
6 | 74LVC2G00-Q100 |
nexperia |
Dual 2-input NAND gate | |
7 | 74LVC2G02 |
NXP |
Dual 2-input NOR gate | |
8 | 74LVC2G02 |
Diodes |
DUAL 2-INPUT NOR GATE | |
9 | 74LVC2G02 |
UTC |
DUAL 2-INPUT POSITIVE-NOR GATE | |
10 | 74LVC2G02 |
nexperia |
Dual 2-input NOR gate | |
11 | 74LVC2G02-Q100 |
NXP |
Dual 2-input NOR gate | |
12 | 74LVC2G02-Q100 |
nexperia |
Dual 2-input NOR gate |