The 74LVC2G00-Q100 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down appli.
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant outputs for interfacing with 5 V logic
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power dissipation
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8-B/JESD36 (2.7 V to 3.6 V)
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Overvoltage toleran.
The 74LVC2G00-Q100 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This fe.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LVC2G00 |
Diodes |
DUAL 2-INPUT NAND GATE | |
2 | 74LVC2G00 |
NXP |
Dual 2-input NAND gate | |
3 | 74LVC2G00 |
nexperia |
Dual 2-input NAND gate | |
4 | 74LVC2G02 |
NXP |
Dual 2-input NOR gate | |
5 | 74LVC2G02 |
Diodes |
DUAL 2-INPUT NOR GATE | |
6 | 74LVC2G02 |
UTC |
DUAL 2-INPUT POSITIVE-NOR GATE | |
7 | 74LVC2G02 |
nexperia |
Dual 2-input NOR gate | |
8 | 74LVC2G02-Q100 |
NXP |
Dual 2-input NOR gate | |
9 | 74LVC2G02-Q100 |
nexperia |
Dual 2-input NOR gate | |
10 | 74LVC2G04 |
nexperia |
Dual inverter | |
11 | 74LVC2G04 |
Diodes |
DUAL INVERTERS | |
12 | 74LVC2G04-Q100 |
nexperia |
Dual inverter |