The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driv.
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 250 mA
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8-B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• MIL-STD-883, met.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LVC1G74 |
nexperia |
Single D-type flip-flop | |
2 | 74LVC1G74 |
NXP Semiconductors |
Single D-type flip-flop | |
3 | 74LVC1G79 |
nexperia |
Single D-type flip-flop | |
4 | 74LVC1G79 |
NXP Semiconductors |
Single D-type flip-flop positive-edge trigger | |
5 | 74LVC1G79-Q100 |
nexperia |
Single D-type flip-flop | |
6 | 74LVC1G00 |
Diodes |
SINGLE 2 INPUT POSITIVE NAND GATE | |
7 | 74LVC1G00 |
nexperia |
Single 2-input NAND gate | |
8 | 74LVC1G00-Q100 |
nexperia |
Single 2-input NAND gate | |
9 | 74LVC1G02 |
Diodes |
SINGLE 2 INPUT POSITIVE NOR GATE | |
10 | 74LVC1G02 |
nexperia |
Single 2-input NOR gate | |
11 | 74LVC1G02-Q100 |
nexperia |
Single 2-input NOR gate | |
12 | 74LVC1G04 |
nexperia |
Single inverter |