74HCT112D - nexperia

74HCT112D Dual JK flip-flop

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flop.

Features

• Input levels:
• For 74HC112: CMOS level
• For 74HCT112: TTL level
• Asynchronous set and reset
• Specified in compliance with JEDEC standard no. 7A
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC112D -40 °C to +125 °C 74HCT112D 74HC112PW -40 °C to +125 °C 74HCT112PW Name SO16 TSSOP16 Description Version plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 plastic thin shri.