The 74HC4040-Q100; 74HCT4040-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter sta.
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• Input levels:
• For 74HC4040-Q100: CMOS level
• For 74HCT4040-Q100: TTL level
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74HC4040 |
Texas Instruments |
12-Bit Asynchronous Binary Counters | |
2 | 74HC4040 |
NXP |
12-stage binary ripple counter | |
3 | 74HC4040 |
nexperia |
12-stage binary ripple counter | |
4 | 74HC4040D |
nexperia |
12-stage binary ripple counter | |
5 | 74HC4046 |
ON |
Phase-Locked Loop | |
6 | 74HC4046 |
Fairchild |
CMOS Phase Lock Loop | |
7 | 74HC4046 |
System Logic |
Phase-Locked Loop | |
8 | 74HC4046A |
nexperia |
Phase-locked loop | |
9 | 74HC4046A |
Philips |
Phase-locked-loop | |
10 | 74HC4049 |
NXP |
Hex inverting HIGH-to-LOW level shifter | |
11 | 74HC4049 |
nexperia |
Hex inverting HIGH-to-LOW level shifter | |
12 | 74HC4049D |
Toshiba |
Hex Buffer |