The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT175 The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs. The common clock (CP) and master reset (MR) inputs load and re.
• Four edge-triggered D flip-flops
• Output capability: standard
• ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT175
The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is trans.
The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complement.
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature complementa.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74HC173 |
Philips |
Quad D-type flip-flop positive-edge trigger | |
2 | 74HC173 |
Texas Instruments |
Quad D-Type Flip-Flop | |
3 | 74HC173 |
nexperia |
Quad D-type flip-flop | |
4 | 74HC173D |
nexperia |
Quad D-type flip-flop | |
5 | 74HC174 |
Texas Instruments |
Hex D-Type Flip-Flops | |
6 | 74HC174 |
Philips |
Hex D-type flip-flop | |
7 | 74HC174 |
nexperia |
Hex D-type flip-flop | |
8 | 74HC174-Q100 |
nexperia |
Hex D-type flip-flop | |
9 | 74HC174D |
nexperia |
Hex D-type flip-flop | |
10 | 74HC175-Q100 |
nexperia |
Quad D-type flip-flop | |
11 | 74HC175AP |
Toshiba Semiconductor |
Quad D-Type Flip-Flop | |
12 | 74HC175D |
Toshiba |
Quad D-Type Flip-Flop |