The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flop.
• Input levels:
• For 74HC112: CMOS level
• For 74HCT112: TTL level
• Asynchronous set and reset
• Specified in compliance with JEDEC standard no. 7A
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information Type number Package
Temperature range
74HC112D
-40 °C to +125 °C
74HCT112D
74HC112PW -40 °C to +125 °C
74HCT112PW
Name SO16
TSSOP16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
plastic thin shri.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74HC112 |
Philips |
Dual JK flip-flop | |
2 | 74HC112 |
Texas Instruments |
Dual J-K Negative-Edge-Triggered Flip-Flops | |
3 | 74HC112 |
nexperia |
Dual JK flip-flop | |
4 | 74HC11 |
Philips |
Triple 3-input AND gate | |
5 | 74HC11 |
Texas Instruments |
Triple 3-Input AND Gate | |
6 | 74HC11 |
NXP |
Triple 3-input AND gate | |
7 | 74HC11 |
nexperia |
Triple 3-input AND gate | |
8 | 74HC11-Q100 |
nexperia |
Triple 3-input AND gate | |
9 | 74HC114 |
Hitachi |
Dual J-K Flip-Flops | |
10 | 74HC11D |
nexperia |
Triple 3-input AND gate | |
11 | 74HC10 |
Philips |
Triple 3-input NAND gate | |
12 | 74HC10 |
Texas Instruments |
Triple 3-Input NAND Gates |