The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-.
• Wide operating voltage range of 2 V to 6 V
• Outputs can drive up to 10 LSTTL loads
• Low power consumption, 40-μA max ICC
• Typical tpd = 13 ns
• ±4-mA output drive at 5 V
• Low input current of 1 μA max
2 Description
The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the .
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP).
The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74HC11 |
Philips |
Triple 3-input AND gate | |
2 | 74HC11 |
Texas Instruments |
Triple 3-Input AND Gate | |
3 | 74HC11 |
NXP |
Triple 3-input AND gate | |
4 | 74HC11 |
nexperia |
Triple 3-input AND gate | |
5 | 74HC11-Q100 |
nexperia |
Triple 3-input AND gate | |
6 | 74HC112D |
nexperia |
Dual JK flip-flop | |
7 | 74HC114 |
Hitachi |
Dual J-K Flip-Flops | |
8 | 74HC11D |
nexperia |
Triple 3-input AND gate | |
9 | 74HC10 |
Philips |
Triple 3-input NAND gate | |
10 | 74HC10 |
Texas Instruments |
Triple 3-Input NAND Gates | |
11 | 74HC10 |
nexperia |
Triple 3-input NAND gate | |
12 | 74HC10-Q100 |
nexperia |
Triple 3-input NAND gate |