The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an .
I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Common 3-state output enable input I Input levels: N For 74AHC374: CMOS level N For 74AHCT374: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C Nexperia 74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package .
74AHC374; 74AHCT374 The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schott.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74AHC373 |
nexperia |
Octal D-type transparant latch | |
2 | 74AHC373 |
NXP |
Octal D-type transparent latch | |
3 | 74AHC374-Q100 |
nexperia |
Octal D-type flip-flop | |
4 | 74AHC374D |
nexperia |
Octal D-type flip-flop | |
5 | 74AHC374PW |
nexperia |
Octal D-type flip-flop | |
6 | 74AHC377 |
nexperia |
Octal D-type flip-flop | |
7 | 74AHC377-Q100 |
nexperia |
Octal D-type flip-flop | |
8 | 74AHC377D |
nexperia |
Octal D-type flip-flop | |
9 | 74AHC377PW |
nexperia |
Octal D-type flip-flop | |
10 | 74AHC30 |
NXP |
8-input NAND gate | |
11 | 74AHC30 |
nexperia |
8-input NAND gate | |
12 | 74AHC30-Q100 |
nexperia |
8-input NAND gate |