The 74AHC374-Q100; 74AHCT374-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC374-Q100; 74AHCT374-Q100 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A.
Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Common 3-state output enable input
Input levels:
For 74AHC374-Q100: CMOS level For 74AHCT374-Q100: TTL level
ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
Nexperia
74AHC374-Q100; 74AHCT374-Q100
Octal D-type flip-f.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74AHC374 |
nexperia |
Octal D-type flip-flop | |
2 | 74AHC374 |
NXP |
Octal D-type flip-flop | |
3 | 74AHC374D |
nexperia |
Octal D-type flip-flop | |
4 | 74AHC374PW |
nexperia |
Octal D-type flip-flop | |
5 | 74AHC373 |
nexperia |
Octal D-type transparant latch | |
6 | 74AHC373 |
NXP |
Octal D-type transparent latch | |
7 | 74AHC377 |
nexperia |
Octal D-type flip-flop | |
8 | 74AHC377-Q100 |
nexperia |
Octal D-type flip-flop | |
9 | 74AHC377D |
nexperia |
Octal D-type flip-flop | |
10 | 74AHC377PW |
nexperia |
Octal D-type flip-flop | |
11 | 74AHC30 |
NXP |
8-input NAND gate | |
12 | 74AHC30 |
nexperia |
8-input NAND gate |