The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the correspon.
s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See ABT377 for clock enable version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT273CSC 74ABT273CSJ 74ABT273CMSA 74ABT273CMTC Package Number M20B M.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74ABT273A |
NXP |
Octal D-type flip-flop | |
2 | 74ABT20 |
NXP |
Dual 4-input NAND gate | |
3 | 74ABT20 |
nexperia |
Dual 4-input NAND gate | |
4 | 74ABT20D |
nexperia |
Dual 4-input NAND gate | |
5 | 74ABT20DB |
nexperia |
Dual 4-input NAND gate | |
6 | 74ABT20PW |
nexperia |
Dual 4-input NAND gate | |
7 | 74ABT2240 |
NXP |
Octal inverting buffer | |
8 | 74ABT2240 |
Fairchild Semiconductor |
Octal Buffer/Line Driver | |
9 | 74ABT2241 |
NXP |
Octal buffers | |
10 | 74ABT2244 |
NXP |
Octal buffer/line driver | |
11 | 74ABT2244 |
Fairchild Semiconductor |
Octal Buffer/Line Driver | |
12 | 74ABT2245 |
NXP |
Octal transceiver |