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4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. Whe.
complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted.
CONNECTION DIAGRAMS DIP (TOP VIEW)
Q0 Q1 Q1 E0
–1 GND Q2 Q2 Q3 16 15 14 13 12 11 10 9
SN54 / 74LS75
1 2 3 4 56 78 Q0 D0 D1 E2
–3 VCC D2 D3 Q3
Q0 Q1 E0
–1 GND NC Q2 Q3 14 13 12 11 10 9 8
SN54 / 74LS77
123456.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | 54LS74 |
National Semiconductor |
Dual Positive-Edge-Triggered D Flip-Flops |
|
| 2 | 54LS74A |
Texas Instruments |
Dual D-Type Positive-Edge -Triggered Flip-Flops |
|
| 3 | 54LS75 |
Motorola |
4-BIT D LATCH |
|
| 4 | 54LS76A |
Texas Instruments |
DUAL J-K FLIP-FLOPS |
|
| 5 | 54LS76A |
Motorola |
DUAL JK FLIP-FLOP |
|
| 6 | 54LS00 |
ETC |
QUAD 2-INPUT NAND GATE |
|
| 7 | 54LS00 |
National Semiconductor |
Quad 2-Input NAND Gates |
|
| 8 | 54LS02 |
National Semiconductor |
Quad 2-Input NOR Gates |
|
| 9 | 54LS03 |
National Semiconductor |
Quad 2-Input NAND Gates |
|
| 10 | 54LS04 |
Motorola |
HEX INVERTER |
|
| 11 | 54LS04 |
National Semiconductor |
Hex Inverting Gates |
|
| 12 | 54LS05 |
National Semiconductor |
HEX INVERTERS |
|