DUAL JK FLIP-FLOP WITH SET AND CLEAR The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times .
f the referenced input (or output) one setup time prior to the HIGH-to-LOW clock transition Q CLEAR (CD) J LOGIC DIAGRAM CLOCK (CP) Q SET (SD) K 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC SYMBOL 27 16 K SD Q 15 12 K SD Q 11 1 CP 6 CP 4 J CD Q 14 9 J CD Q 10 3 VCC = PIN 5 GND = PIN 13 8 FAST AND LS TTL DATA 5-1 SN54 / 74LS76A GUARANTEED OPERATING RANGES Symbol Parameter VCC Supply Voltage TA Operating Ambient Temperature Range Min Ty.
SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 19.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 54LS74 |
National Semiconductor |
Dual Positive-Edge-Triggered D Flip-Flops | |
2 | 54LS74A |
Texas Instruments |
Dual D-Type Positive-Edge -Triggered Flip-Flops | |
3 | 54LS75 |
Motorola |
4-BIT D LATCH | |
4 | 54LS77 |
Motorola |
4-BIT D LATCH | |
5 | 54LS00 |
ETC |
QUAD 2-INPUT NAND GATE | |
6 | 54LS00 |
National Semiconductor |
Quad 2-Input NAND Gates | |
7 | 54LS02 |
National Semiconductor |
Quad 2-Input NOR Gates | |
8 | 54LS03 |
National Semiconductor |
Quad 2-Input NAND Gates | |
9 | 54LS04 |
Motorola |
HEX INVERTER | |
10 | 54LS04 |
National Semiconductor |
Hex Inverting Gates | |
11 | 54LS05 |
National Semiconductor |
HEX INVERTERS | |
12 | 54LS06 |
Texas Instruments |
Hex Inverter Buffers/Drivers |