ICS9LP525-2 |
Part Number | ICS9LP525-2 |
Manufacturer | Integrated Device Technology |
Description | PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request cont... |
Features |
• 2 - CPU differential low power push-pull pairs • 7- SRC differential low power push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 5 - PCI, 33MHz • 1 - PCI_F, 33MHz free running • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on all outputs • SRC are PCIe Gen2 compliant ICS9LP525-2 Features/Benefits: • Supports spread spectrum modulation,... |
Document |
ICS9LP525-2 Data Sheet
PDF 269.62KB |
Distributor | Stock | Price | Buy |
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No. | Parte # | Fabricante | Descripción | Hoja de Datos |
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1 | ICS9LP525-2 |
Renesas |
56-pin CK505 Clock | |
2 | ICS9LPR426A |
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3 | ICS9LPR501 |
ICS |
64-pin CK505 w/Fully Integrated Voltage Regulator | |
4 | ICS9LPR501 |
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5 | ICS9LPRS365 |
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