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M13S128168A |
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| Part Number | M13S128168A |
| Manufacturer | Elite Semiconductor Memory Technology |
| Description | (M13S128168A) Pin Name Function Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address ... |
| Features |
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M13S128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data... |
| Document |
 M13S128168A Data Sheet
PDF 716.99KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | M13S128324A |
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| 2 | M13S2561616A |
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4M x 16 Bit x 4 Banks Double Data Rate SDRAM |
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| 3 | M13S256328A |
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2M x 32 Bit x 4 Banks Double Data Rate SDRAM |
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| 4 | M13S32321A |
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| 5 | M13S5121632A |
ESMT |
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