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ZL30116 |
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| Part Number | ZL30116 |
| Manufacturer | Zarlink Semiconductor |
| Description | . . . . 12 1.1 DPLL Features.. .... |
| Features |
• Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz • Provides two DPLLs which are independently configurable through a serial software interface • DPLL1 provides all the features necessary for generating ... |
| Document |
 ZL30116 Data Sheet
PDF 381.04KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | ZL30110 |
Zarlink Semiconductor |
Telecom Rate Conversion DPLL |
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| 2 | ZL30111 |
Zarlink Semiconductor |
POTS Line Card PLL |
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| 3 | ZL30112 |
Zarlink Semiconductor |
SLIC/CODEC DPLL |
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| 4 | ZL30117 |
Zarlink Semiconductor |
SONET/SDH Low Jitter Line Card Synchronizer |
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| 5 | ZL30119 |
Zarlink Semiconductor |
Low Jitter Line Card Synchronizer |
|