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74LS107 |
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| Part Number | 74LS107 |
| Manufacturer | ETC |
| Description | This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock ... |
| Features |
N See NS Package Number J14A M14A N14A or W14B
Function Table
Inputs CLR L H H H H H CLK X J X L H L H X K X L L H H X Q L Q0 H L Toggle Q0 Q0 Outputs Q H Q0 L H
v v v v
H
H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level
v e Negative going edge of pulse
Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse
C1995 National Semiconductor Corporation
TL F 6367
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
If Mili... |
| Document |
 74LS107 Data Sheet
PDF 143.69KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | 74LS10 |
ON Semiconductor |
TRIPLE 3-INPUT NAND GATE |
|
| 2 | 74LS10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate |
|
| 3 | 74LS109 |
Agere Systems |
Dual J-K Flip-Flop |
|
| 4 | 74LS109A |
ON Semiconductor |
LOW POWER SCHOTTKY |
|
| 5 | 74LS109A |
Texas Instruments |
Dual J-K Positive-Edge-Triggered Flip-Flops |
|