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IS61DDP2B21M36A |
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| Part Number | IS61DDP2B21M36A |
| Manufacturer | Integrated Silicon Solution |
| Description | 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write oper... |
| Features |
DESCRIPTION
1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used... |
| Document |
 IS61DDP2B21M36A Data Sheet
PDF 516.69KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | IS61DDP2B21M36A1 |
Integrated Silicon Solution |
36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
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| 2 | IS61DDP2B21M36A2 |
Integrated Silicon Solution |
36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM |
|
| 3 | IS61DDP2B21M36C |
ISSI |
36Mb DDR-IIP CIO SYNCHRONOUS SRAM |
|
| 4 | IS61DDP2B21M36C1 |
ISSI |
36Mb DDR-IIP CIO SYNCHRONOUS SRAM |
|
| 5 | IS61DDP2B21M36C2 |
ISSI |
36Mb DDR-IIP CIO SYNCHRONOUS SRAM |
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