IS61DDP2B21M36A2 - Integrated Silicon Solution

IS61DDP2B21M36A2 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM

 1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock s.

Features

DESCRIPTION
 1Mx36 and 2Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Common I/O read and write ports.
 Synchronous pipeline read with self-timed late write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 2.0 cycle read latency.
 Fixed 2-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
 +1.8V core power supply and 1.5, 1.8V VDDQ, used.