| No. | Partie # | Fabricant | Description | Fiche Technique |
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Siemens |
TVTEXT 8-Bit Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Configurations . . . . . . . . . . |
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Siemens |
Memory Sync Controller III Large area flicker elimination through field doubling Additional elimination of interline flicker in field mode Field switching and selection in field mode Noise and cross-color reduction Stills 9-image display, still-in-picture, picture-in-still wit |
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Siemens |
Nonvolatile Memory 1-Kbit E2PROM q Word-organized reprogrammable nonvolatile memory q q q q q q q q q in n-channel floating-gate technology (E2PROM) 128 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/wri |
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Siemens |
Nonvolatile Memory 2-Kbit E2PROM with I2C Bus q Word-organized programmable nonvolatile memory in q q q q q q q q q n-channel floating-gate technology (E2PROM) 256 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write |
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Siemens Semiconductor |
FREQUENCY DIVIDER 1:64 |
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Siemens |
ICs for Consumer Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . |
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Siemens |
8 Bit Microcpntroller |
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siemens |
SDA4330-2X 155 MHz FM and 40 MHz AM input frequency 30 mVeff AM and 50 mVeff FM sensitivity 16 bit IF counter up to 50 MHz Additional open drain ports controlled by I2C 2-pin quartz oscillator P-DSO-24-1 Fast phase detector with short anti-backlash pulses and |
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Siemens |
1-Chip-VPS-Decoder µC SDA 5642 SDA 5642X MOS IC suitable VPS data editing direct from CVBS signal n-channel MOS Generating of the line synchronous 5-MHz clock for the time base and data clock by means of PLL operation Very few external components necessary Adaptative |
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Siemens Semiconductor |
120 MHz PLL for AM/FM Receivers |
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Siemens |
IR REMOTE CONTROL TRANSMITTER WITH IR DIODE DRIVER |
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Siemens |
Nonvolatile Memory 2-Kbit E2PROM with I2C Bus q Word-organized programmable nonvolatile memory in q q q q q q q q q n-channel floating-gate technology (E2PROM) 256 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write |
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Siemens |
1.3 GHZ PLL WITH I2C BUS |
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Siemens |
TVTEXT 8-Bit Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Configurations . . . . . . . . . . |
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Siemens |
Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder q Single-chip receiver for PDC data, broadcast either q q q q q q q q q q q – in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or – in dedicated line no. 16 of the vertical blanking interval (VPS) Reception of Uni |
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Siemens |
Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder q Single-chip receiver for PDC data, broadcast either q q q q q q q q q q q q – in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or – in dedicated line no. 16 of the vertical blanking interval (VPS) Reception of |
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Siemens |
TV SAT PLL WITH I2C BUS AND FOUR CHIP ADDRESSES |
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Siemens |
Picture-in-Picture Processor with On-Chip PLL q On-chip PLL q Full frame display for 50/60 Hz in order to increase the vertical resolution and to suppress moving artifacts. q Compatibility to the 16:9 display format by means of q q q q q q independent setting of the vertical and horizontal d |
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Siemens |
Triple 8-Bit Analog-to-Digital-Converter Three equivalent CMOS A/D converters on chip 30-MHz sample rate 8-bit resolution No external sample & hold required On-chip input buffer for each analog channel Internal clamping circuits for each of the ADCs Different digital output multiplex format |
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Siemens |
868352-Bit Dynamic Sequential Access Memory for Television Applications (TV-SAM) q q q q q q q q q q q q q q q q q CMOS IC 212 x 64 x 16 x 4-bit organization Triple port architecture One 16 x 4-bit input shift register Two 16 x 4-bit output shift registers Shift registers independently and simultaneously accessible Continuous d |
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