No. | Partie # | Fabricant | Description | Fiche Technique |
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Panasonic |
8-bit Microcomputers |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic |
NMOS Nonvolatile Electrically Alterable ROM |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic |
8-bit single-chip microcomputers |
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Panasonic |
Microcomputers |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic Semiconductor |
Lower limit for operation guarantee 4, 1/16, 1/32, 1/64 of OSC oscillation clock frequency; 1/1 of XI oscillation clock frequency; external clock input Interrupt source · · · · · · · · · · · · · · · · coincidence with compare register 0 Timer counter 1 : 8-bit × 1 (square-wave output, event count, sy |
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Panasonic |
MICROCOMPUTER |
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Panasonic |
Microcomputer Manual 1.3 Pin Assignment 1.4 Pin Descriptions 1.5 Unused Pins 1.6 Block Diagram 1.7 Electrical Characteristics 1.8 Package CHAPTER 2 CPU CORE FUNCTIONS 2.1 Clock Generator and CPU Basic Timing 2.2 ROM and RAM 2.3 Stack Area 2.4 Flag Status 2.5 Backup Mode |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic |
32-bit microcontroller provides an easy means of developing low-cost, high-performance and multifunctional system on LSI for motor and power control applications requiring fast response |
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Panasonic |
Microcontroller |
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Panasonic |
Microcontroller |
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Panasonic |
8-bit single-chip microcomputers |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic Semiconductor |
32-bit Single-chip Microcontroller CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max) |
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Panasonic |
Microcomputers/Controllers |
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