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Power logic 8-bit shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset input (MR). A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the |
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nexperia |
Power logic 8-bit shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset input (MR). A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the |
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nexperia |
Power logic 8-bit shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the s |
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nexperia |
Power logic 8-bit shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the s |
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nexperia |
Power logic 8-bit shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the s |
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nexperia |
Power logic 12-bit shift register and benefits Specified from 40 C to +125 C Low RDSon 12 Power EDNMOS transistor outputs of 100 mA continuous current 250 mA current limit capability Output clamping voltage 33 V 30 mJ avalanche energy capability Low power consumption |
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Power logic 12-bit shift register and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +125 C Low RDSon 12 Power EDNMOS transistor outputs of 100 mA continuous current 250 mA current limit capability Output clamping |
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nexperia |
Power logic 8-bit shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the s |
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