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etcTI SN1 DataSheet

No. Partie # Fabricant Description Fiche Technique
1
SN10502

Texas Instruments
HIGH-SPEED RAIL-TO-RAIL OUTPUT VIDEO AMPLIFIERS
1
•2 High Speed
  – 100 MHz Bandwidth (
  –3 dB, G = 2)
  – 900 V/s Slew Rate
• Excellent Video Performance
  – 50 MHz Bandwidth (0.1 dB, G = 2)
  – 0.007% Differential Gain
  – 0.007 Differential Phase
• Rail-to-Rail Output Swing
  – VO =
  –4.5 / 4.5 (RL= 150 Ω)
Datasheet
2
SN10501

Texas Instruments
HIGH-SPEED RAIL-TO-RAIL OUTPUT VIDEO AMPLIFIERS
1
•2 High Speed
  – 100 MHz Bandwidth (
  –3 dB, G = 2)
  – 900 V/s Slew Rate
• Excellent Video Performance
  – 50 MHz Bandwidth (0.1 dB, G = 2)
  – 0.007% Differential Gain
  – 0.007 Differential Phase
• Rail-to-Rail Output Swing
  – VO =
  –4.5 / 4.5 (RL= 150 Ω)
Datasheet
3
SN10KHT5573

Texas Instruments
Octal ECL-to-TTL Translator
N10KHT5573 are transparent D-type latches. While latch enable (LE) is low, the Q outputs follow the data (D) inputs. When LE is high, the Q outputs are latched at the levels that were set up at the D inputs. A buffered output-enable (OE) input can be
Datasheet
4
SN10KHT5539

Texas Instruments
Octal ECL-to-TTL Translator
smitters while eliminating the need for 3-state overlap protection. Two pins OE1 and OE2 are provided for output-enable control. These control inputs are ANDed together with OE1 being ECL-compatible and OE2 being TTL-compatible. This offers the choic
Datasheet
5
SN10KHT5538

Texas Instruments
Octal ECL-to-TTL Translator
gnal environment. The SN10KHT5538 is characterized for operation from 0°C to 75°C. SN10KHT5538 OCTAL ECLĆTOĆTTL TRANSLATOR WITH OPENĆCOLLECTOR OUTPUTS SDZS012 − MARCH 1990 DW OR NT PACKAGE (T0P VIEW) Y1 Y2 Y3 Y4 VCC GND GND GND Y5 Y6 Y7 Y8 1 2 3 4
Datasheet
6
SN10KHT5543

Texas Instruments
Octal ECL-to-TTL Translator
UM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device SN10KHT5543DW Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) Lead/Ball Finish (6) NIPDAU MSL Peak Temp Op T
Datasheet
7
SN105125

Texas Instruments
150-mA Low Dropout Regulator
D Low Dropout Voltage Regulator, 1.2-V D 150-mA Load Current Capability D Power Okay (POK) Function D Load Independent, Low Ground Current,150-µA D Current Limiting D Thermal Shutdown D Low Sleep State Current (Off Mode) D Fast Transient Response D L
Datasheet
8
SN10503

Texas Instruments
HIGH-SPEED RAIL-TO-RAIL OUTPUT VIDEO AMPLIFIERS
1
•2 High Speed
  – 100 MHz Bandwidth (
  –3 dB, G = 2)
  – 900 V/s Slew Rate
• Excellent Video Performance
  – 50 MHz Bandwidth (0.1 dB, G = 2)
  – 0.007% Differential Gain
  – 0.007 Differential Phase
• Rail-to-Rail Output Swing
  – VO =
  –4.5 / 4.5 (RL= 150 Ω)
Datasheet
9
SN10KHT5578

Texas Instruments
Octal ECL-to-TTL Translator
L) 19 VCC 18 VEE 17 CLK(TTL) 16 5D 15 6D 14 7D 13 8D The eight flip-flops of the ’5578 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs. The ou
Datasheet
10
SN10KHT5540

Texas Instruments
Octal ECL-to-TTL Translator
T ENABLE OE1 OE2 XH HX LL LL DATA INPUT A X X L H OUTPUT (TTL) Y Z Z H L SN10KHT5540 OCTAL ECLĆTOĆTTL TRANSLATOR WITH 3ĆSTATE OUTPUTS SDZS006 − DECEMBER 1990 DW OR NT PACKAGE (T0P VIEW) Y1 Y2 Y3 Y4 VCC GND GND GND Y5 Y6 Y7 Y8 1 2 3 4 5 6 7 8 9 1
Datasheet
11
SN10KHT5541

Texas Instruments
Octal ECL-to-TTL Translator
TPUT ENABLE OE1 OE2 XH HX LL LL DATA INPUT A X X L H OUTPUT (TTL) Y Z Z L H SN10KHT5541 OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS SDZS003A
  – OCTOBER 1989
  – REVISED OCTOBER 1990 DW OR NT PACKAGE (T0P VIEW) Y1 Y2 Y3 Y4 VCC GND GND GND Y5 Y6
Datasheet
12
SN10KHT5542

Texas Instruments
Octal ECL-to-TTL Translator
UM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device SN10KHT5543DW Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) Lead/Ball Finish (6) NIPDAU MSL Peak Temp Op T
Datasheet
13
SN10KHT5574

Texas Instruments
Octal ECL-to-TTL Translator
0KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs. A buffered output-enable input (OE) can be used to place the eight outputs in either
Datasheet



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