| No. | Partie # | Fabricant | Description | Fiche Technique |
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Texas Instruments |
Low-Jitter Crystal Oscillator Clock Generator 1 •2 Single 3.3-V Supply • High-Performance Clock Generator, Incorporating Crystal Oscillator Circuitry with Integrated Frequency Synthesizer • Low Output Jitter: As low as 380 fs (RMS integrated between 10 kHz to 20 MHz) • Low Phase Noise at 312.5 M |
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Texas Instruments |
Flexible Low Power LVCMOS Clock Generator • Member of programmable clock generator family – CDCE913/CDCEL913: 1-PLL, 3 outputs – CDCE925/CDCEL925: 2-PLL, 5 outputs – CDCE937/CDCEL937: 3-PLL, 7 outputs – CDCE949/CDCEL949: 4-PLL, 9 outputs • In-system programmability and EEPROM – Serial progra |
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Texas Instruments |
High-Performance Clock 2:8 Buffer •1 2:8 Differential Buffer • Selectable Clock Inputs Through Control terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Eight LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 73 mA • Very Low Additi |
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Texas Instruments |
Flexible Low Power LVCMOS Clock Generator • Member of programmable clock generator family – CDCE913/CDCEL913: 1-PLL, 3 outputs – CDCE925/CDCEL925: 2-PLL, 5 outputs – CDCE937/CDCEL937: 3-PLL, 7 outputs – CDCE949/CDCEL949: 4-PLL, 9 outputs • In-system programmability and EEPROM – Serial progra |
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Texas Instruments |
3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER 1 • Qualified for Automotive Applications • Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose Applications • Spread-Spectrum Clock Compatible • Operating Frequency: 24 MHz to 200 MHz • Low Jitter (Cycle-to-Cycle): <150 ps Over t |
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Texas Instruments |
1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output • Low-Output Skew 15 ps (Typical) for Clock-Distribution A |
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Texas Instruments |
2:16 Low Additive Jitter LVDS Buffer 1 • 2:16 Differential Buffer • Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz • Low Output Skew of 55 ps (Max) • Universal Inputs Accept LVDS, LVPECL, LVCMOS • Selectable Clock Inputs Through Control Pin • 16 LVDS Outputs, ANSI EIA/TIA-644A Sta |
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Texas Instruments |
3.3-V Phase-Lock-Loop Clock Driver 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCC 4Y3 GND VCC 4Y2 GND VCC 4Y1 GND GND VCC 3Y3 GND GND 2Y2 VCC GND 2Y3 VCC GND GND 3Y1 VCC GND 3Y2 VCC de |
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Texas Instruments |
3.3-V Phase-Lock-Loop Clock Driver • Low Output Skew for Clock-Distribution and Clock-Generation Applications • Operates at 3.3-V VCC • Distributes One Clock Input to Six Outputs • One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency • No Exte |
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Texas Instruments |
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER 1 • High-Performance 1:10 Clock Driver • Pin-to-Pin Skew < 100 ps at VDD 3.3 V • VDD Range = 2.3 V to 3.6 V • Input Clock Up To 200 MHz (See Figure 7) • Operating Temperature Range –40°C to 85°C • Output Enable Glitch Suppression • Distributes One Cl |
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Texas Instruments |
2:8 Low Additive Jitter LVDS Buffer •1 2:8 Differential Buffer • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz • Low Output Skew of 45 ps (Maximum) • Universal Inputs Accept LVDS, LVPECL, and LVCMOS • Selectable Clock Inputs Through Control Pin • 8 LVDS Outputs, ANSI EIA/TIA-64 |
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Texas Instruments |
Flexible Low Power LVCMOS Clock Generator •1 Member of Programmable Clock Generator Family – CDCEx913: 1 PLLs, 3 Outputs – CDCEx925: 2 PLLs, 5 Outputs – CDCEx937: 3 PLLs, 7 Outputs – CDCEx949: 4 PLLs, 9 Outputs • In-System Programmability and EEPROM – Serial Programmable Volatile Register – |
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Texas Instruments |
THREE PLLs BASED CLOCK GENERATOR • High Performance Clock Generator • Clock Input Compatible With LVCMOS/LVTTL • Requires a 54-MHz Input Clock to Generate Multiple Output Frequencies • Low Jitter for Clock Distribution • Generates the Following Clocks: – VIDCLK 74.175824 MHz/54 MHz |
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Texas Instruments |
3.3-V Phase-Lock-Loop Clock Driver 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCC 4Y3 GND VCC 4Y2 GND VCC 4Y1 GND GND VCC 3Y3 GND GND 2Y2 VCC GND 2Y3 VCC GND GND 3Y1 VCC GND 3Y2 VCC NC – No |
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Texas Instruments |
CRYSTAL-OSCILLATOR CLOCK GENERATOR • Single 3.3 V Supply • High-Performance Clock Generator, Incorporating Crystal Oscillator Circuitry With Integrated Frequency Synthesizer • Low Output Jitter, as Low as 380 fs (rms integrated between 10 kHz –20 MHz) • Low Phase Noise at 312.5 MHz, Le |
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Texas Instruments |
3.3-V Phase-Lock-Loop Clock Driver 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCC 4Y3 GND VCC 4Y2 GND VCC 4Y1 GND GND VCC 3Y3 GND GND 2Y2 VCC GND 2Y3 VCC GND GND 3Y1 VCC GND 3Y2 VCC |
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Texas Instruments |
3.3-V Phase-Lock-Loop Clock Driver 2Y1 19 GND 18 GND 17 2Y2 16 2Y3 15 VCC 14 2G 13 FBIN description The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) ou |
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Texas Instruments |
3.3-V PHASE-LOCK LOOP CLOCK DRIVER 1 • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 • Spread Spectrum Clock Compatible • Operating Frequency 20 MHz to 175 MHz • Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps • Jitter (cyc –cyc) at 66 M |
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Texas Instruments |
High-Performance Clock Buffer •1 2:12 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • 12 LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 88 mA • Very Low Additive |
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Texas Instruments |
PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER 1 • Qualified for Automotive Applications • Member of Programmable Clock Generator Family – CDCE913/CDCEL913: 1 PLLs, 3 Outputs – CDCE925/CDCEL925: 2 PLLs, 5 Outputs – CDCE937/CDCEL937: 3 PLLs, 7 Outputs – CDCE949: 4 PLLs, 9 Outputs • In-System Progr |
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