| No. | Partie # | Fabricant | Description | Fiche Technique |
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Texas Instruments |
18-Bit Registered Transceivers • FCT-C speed at 4.6 ns • Ioff supports partial-power- mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages |
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ETCTI |
BiCMOS 9-Bit Bus-Interface D-Type Latch With 3-State Outputs |
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Texas Instruments |
20-Bit Latches • FCT-C speed at 5.5 ns (FCT16841T Com’l) • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP ( |
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Texas Instruments |
OCTAL BUS TRANSCEIVERS 0A – MARCH 1987 – REVISED OCTOBER 1993 SN54F245 . . . J PACKAGE SN74F245 . . . DB, DW, OR N PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 OE 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8 SN54F245 . . . FK PAC |
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Texas Instruments |
18-Bit Registers • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temper |
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Texas Instruments |
16-Bit Buffers/Line Drivers • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temper |
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Texas Instruments |
8-BIT LATCHED TRANSCEIVER 3 OEAB description The CY74FCT2543T octal latched transceiver contains two sets of eight D-type latches. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs permit each latch set to have independent control of inputting and out |
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Texas Instruments |
8-BIT BUFFERS/LINE DRIVERS 0 OEA VCC OEB DA1 OB1 DA2 OB2 DA3 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 OA0 DB0 OA1 DB1 OA2 OB 3 GND DB 3 OA 3 DB 2 description The ’FCT244T devices are octal buffers and line drivers designed to be employed as memory address driver |
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Texas Instruments |
18-Bit Registered Transceivers • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages • Industrial temper |
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Texas Instruments |
20-Bit Buffers/Line Drivers • Ioff Supports Partial-Power-Down Mode Operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temper |
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Texas Instruments |
18-Bit Registered Transceivers • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages • Industrial temper |
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Texas Instruments |
QUAD 2-INPUT MULTIPLEXER , and the I1 inputs are selected when S is high. Data at the output is noninverted. The CY74FCT257T is a logic implementation of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. Outputs are in |
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Texas Instruments |
Octal Transceiver the data flow through the bidirectional transceivers. When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port from the B port. When the output enable (OE) input is high, both the A and B p |
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Texas Instruments |
QUADRUPLE 2-INPUT POSITIVE-NOR GATES 14 VCC 13 4Y 12 4B 11 4A 10 3Y 9 3B 8 3A SN54F02 . . . FK PACKAGE (TOP VIEW) VCC 4Y 1B 3 2 1 20 19 4 18 4B NC 5 17 NC 2Y 6 16 4A NC 7 15 NC 2A 8 14 3Y 9 10 11 12 13 NC NC GND 1Y 2B 1A 3A 3B NC – No internal connection 1 1Y 4 2Y 1 |
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Texas Instruments |
10-BIT BUS-INTERFACE REGISTER packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT821T is a 10-bit-wide buffered version of the popular CY74FCT374 function. This device is ideal for use as |
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Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATE 1Y 11 3C 10 3B 9 3A 8 3Y SN54F10 . . . FK PACKAGE (TOP VIEW) 1C VCC NC 1A 1B 2A 3 2 1 20 19 4 18 1Y NC 5 17 NC 2B 6 16 3C NC 7 15 NC 2C 8 14 3B 9 10 11 12 13 3A 3Y NC GND 2Y NC – No internal connection logic diagram, each ga |
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Texas Instruments |
QUADRUPLE 2-INPUT POSITIVE-OR GATES – No internal connection ≥1 3 1Y 6 2Y 8 3Y 11 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram, each gate (positive logic) A Y B Pleas |
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ETCTI |
BiCMOS Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs |
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Texas Instruments |
Octal Buffer/Driver lications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments |
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Texas Instruments |
8-BIT REGISTERS to the corresponding flip-flop’s Q output. All outputs are forced low by a low logic level on the MR input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging c |
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