| No. | Partie # | Fabricant | Description | Fiche Technique |
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Texas Instruments |
8-BIT PARALLEL-LOAD SHIFT REGISTER gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for seri |
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Texas Instruments |
8-BIT PARALLEL-LOAD SHIFT REGISTER gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or C D CLK INH CLK GND 4 5 6 7 8 13 QH 12 G 11 F 10 E 9 CLR serial-in modes are established by the shift / load (SH/LD) input. When high, SH/LD enables the se |
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Texas Instruments |
SoC 1 • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With – 1.0 GHz or 1.2 GHz C66x Fixed- and FloatingPoint DSP Core – 38.4 GMacs/Core for Fixed Point @ 1.2 GHz – 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Memory – 32-KB L1P Per CoreP |
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Texas Instruments |
SoC 1 • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With – 1.0 GHz or 1.2 GHz C66x Fixed- and FloatingPoint DSP Core – 38.4 GMacs/Core for Fixed Point @ 1.2 GHz – 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Memory – 32-KB L1P Per CoreP |
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Texas Instruments |
SoC and Description 1.1 Features 1 • ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Se |
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Texas Instruments |
Parallel-Load 8-Bit Shift Registers 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for P |
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Texas Instruments |
3.5-mm Jack Detect and Headset Interface •1 Ultra Low-Power, High-Performance DirectPath™ Class-G Headphone Amplifier – Ground-Centered Output Eliminates DCBlocking Capacitors – 30 mW/Ch into 32 Ω / Ch at 1% THD+N – –42 dB to +6 dB Volume Control – 2.0 µV Output Noise at –42 dB Gain – 91-dB |
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Texas Instruments |
25-Bit Configurable Registered Buffer 1 •2 Member of the Texas Instruments Widebus+™ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer • Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consu |
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Texas Instruments |
Multicore DSP+Arm KeyStone-II System-on-Chip 1Processor cores: • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHz – Supports full Implementation of Armv7-A architecture instruction set – Integrated SIMDv2 ( Arm® Neon™ Technology) and VFPv4 (Vector Floating Point) – 32K |
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Texas Instruments |
SoC and Description 1.1 Features 1 • ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Se |
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Texas Instruments |
SoC 1 • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With – 1.0 GHz or 1.2 GHz C66x Fixed- and FloatingPoint DSP Core – 38.4 GMacs/Core for Fixed Point @ 1.2 GHz – 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Memory – 32-KB L1P Per CoreP |
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Texas Instruments |
SoC and Description 1.1 Features 1 • Four TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With – 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point DSP Core • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz • 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Mem |
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Texas Instruments |
POWER-DISTRIBUTION SWITCHES 1 •2 70-mΩ High-Side MOSFET • 1-A Continuous Current • Thermal and Short-Circuit Protection • Accurate Current-Limit (1.2 A min, 2 A max) • Operating Range: 2.7 V to 5.5 V • 0.6-ms Typical Rise Time • Undervoltage Lockout • Deglitched Fault Report (O |
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Texas Instruments |
4A Processor Supply 1 •2 4A Peak Output Current • Highest Efficiency: – Low RDS,on Switch and Active Rectifier – Power Save Mode for Light Loads • I2C High Speed Compatible Interface • Programmable Output Voltage for Digital Voltage Scaling – 0.5V to 1.77V, 10mV Steps • |
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Texas Instruments |
Parallel-Load 8-Bit Shift Registers 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for P |
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Texas Instruments |
8-BIT PARALLEL-LOAD SHIFT REGISTER gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for seri |
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Texas Instruments |
Hex Bus Driver POST-PLATE POST-PLATE SNPB SNPB SNPB SNPB POST-PLATE POST-PLATE SNPB SNPB POST-PLATE POST-PLATE SNPB SNPB Addendum-Page 1 9-Oct-2020 MSL Peak Temp Op Temp (°C) (3) N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 |
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Texas Instruments |
Polyphase Metering SoCs 1 • Accuracy < 0.1% Over 2000:1 Dynamic Range for Phase Current • Meets or Exceeds ANSI C12.20 and IEC 62053 Standards • Support for Multiple Sensors Such as Current Transformers, Rogowski Coils, or Shunts • Power Measurement for up to Three Phases P |
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Texas Instruments |
8-BIT PARALLEL-LOAD SHIFT REGISTER gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for seri |
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Texas Instruments |
Hex Bus Driver POST-PLATE POST-PLATE SNPB SNPB SNPB SNPB POST-PLATE POST-PLATE SNPB SNPB POST-PLATE POST-PLATE SNPB SNPB Addendum-Page 1 9-Oct-2020 MSL Peak Temp Op Temp (°C) (3) N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 |
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