No. | Partie # | Fabricant | Description | Fiche Technique |
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WILLAS |
NPN Digital Transistor eatures • Batch process design, excellent power dissipation offers Package outline SOT-23 • Pb-Fr •eLbeoewtpteaprrcrokefvialeegrsseuerilfseaacakevamagioeluacnbutrleredenatpapnlidcathtieornmianlorredseisrttaonce. SOD-123H .063(1.60) .047(1.20) RoH |
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WILLAS |
NPN Digital Transistor eatures • Batch process design, excellent power dissipation offers Package outline • Pb-Frebeepttearcrkeavegreseisleaakvaagielacbulrerent and thermal resistance. RoHS • pLoropowtidmpuirzcoetfiblfeoorsaurpdrafascpckeaincmego. ucnotdeed aspupflfiicxa” |
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WILLAS |
NPN Digital Transistor • Batch process design, excellent power dissipation offers better reverse leakage current and thermal resistance. • Low profile surface mounted application in order to optimize board space. • Low power loss, high efficiency. • High current capability |
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WILLAS |
NPN Digital Transistor • Batch process design, excellent power dissipation offers better reverse leakage current and thermal resistance. • Low profile surface mounted application in order to Featuresoptimize board space. • Low power loss, high efficiency. • Pb-Free •pHai |
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WILLAS |
NPN Digital Transistor • Batch process design, excellent power dissipation offers better reverse leakage current and thermal resistance. • Low profile surface mounted application in order to optimize board space. • Low power loss, high efficiency. Features • High curr |
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WILLAS |
NPN Digital Transistor Package outline Features • Batch process design, excellent power dissipation offers better reverse leakage current and thermal resistance. • Pb-Fre • eLooppwtiampcirzkoeafiblgeoesauridsrfasapcveaacmeilo.aubnlteed application in order to SOSD-O123TH |
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WILLAS |
NPN Digital Transistor • Batch process design, excellent power dissipation offers better reverse leakage current and thermal resistance. • Low profile surface mounted application in order to optimize board space. • Low power loss, high efficiency. Features • High curre |
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WILLAS |
NPN Digital Transistor Package outline • Batch process design, excellent power dissipation offers .004(0.10)MIN. .096(2.45) .078(2.00) Featuresbetter reverse leakage current and thermal resistance. • Low profile surface mounted application in order to • Pb-Freeoppatimc |
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WILLAS |
NPN Digital Transistor eatures • Batch process design, excellent power dissipation offers Package outline • Pb-F •reLbeoewtpteparrcroekfvialeegrsseuerilfseaacakevamagoeiluacnubtrelrede nt and thermal resistance. application in order to SSOOD-1T23-H323 .004(0.10)MIN. . |
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WILLAS |
NPN Digital Transistor eatures • Batch process design, excellent power dissipation offers • Pb-Frebeetptearcrekvaegrseeilseaakvagaeilcaubrrleent and thermal resistance. RoHS • Lpooprowtimdpuirzoceftiblfeoosarurpdrfaascpceakcimnego. ucnoteddeapspulfifciaxti”oGn ”in order to |
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WILLAS |
NPN Surface Mount Transistors Simplifies Circuit Design Reduces Board Space Reduces Component Count The SOT-723 Package can be Soldered using Wave or Reflow These are Pb-Free Devices SOT-723 PACKAGE Marking : 3 8C M 3 12 8C = Specific Device Code M = Date Code 1 |
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