| No. | Partie # | Fabricant | Description | Fiche Technique |
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WEDC |
Ruggedized 5.0 Display Head Assembly Dual Mode NTSC (M) and PAL F Timing for RGB Video and NTSC Timing for Composite Video Supports Two Sets of Analog RGB Video Signals NTSC Composite or S-Video Signals Display Resolution 320 x 234 (NTSC) and 320 x 273 (PAL) External Clock Mode Pin1 Du |
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WEDC |
512Kx32 Flash 512Kx32, 2x512Kx32 and 4x512Kx32 Densities Based on AMDs - AM290F040 Flash Device Fast Read Access Time - 80-150ns 5- Volt-Only Reprogramming Sector Erase Architecture Uniform sectors of 64 Kbytes each Any combination of sectors can be |
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WEDC |
64Kx32 CMOS High Speed 64Kx32 bit CMOS Static Random Access Memory Array Fast Access Times: 12*, 15, 20, and 25ns Individual Byte Selects User Configurable Organization with Minimal Additional Logic 64Kx32 CMOS High Speed Static RAM The EDI8L3265C is a high speed, |
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WEDC |
128Kx32 SSRAM/1Mx32 SDRAM DESCRIPTION n Clock speeds: • SSRAM: 200, 166,150, and 133 MHz • SDRAMs: 125 and 100 MHz n n n n n n n DSP Memory Solution • Texas Instruments TMS320C6201 • Texas Instruments TMS320C6701 Packaging: • 153 pin BGA, JEDEC MO-163 3.3V Operating supply |
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WEDC |
RUGGEDIZED 5.6 DISPLAY HEAD ASSEMBLY Dual Mode NTSC (M) and PAL F Timing for RGB Video and NTSC Timing for Composite Video Supports Two Sets of Analog RGB Video Signals NTSC Composite or S-Video Signals Display Resolution 320 x 234 (NTSC) and 320 x 273 (PAL) Scan Reversal External Clock |
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