| No. | Partie # | Fabricant | Description | Fiche Technique |
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Toshiba Semiconductor |
Quad 2-Input OR Gate to 150 °C Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the signif |
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Toshiba Semiconductor |
QUAD BILATERAL SWITCH |
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Toshiba Semiconductor |
QUAD EXCLUSIVE-OR GATE erature range VDD VIN VOUT IIN PD Topr Tstg VSS − 0.5 to VSS + 20 V VSS − 0.5 to VDD + 0.5 V VSS − 0.5 to VDD + 0.5 V ±10 mA 300 (DIP)/180 (SOIC) mW −40 to 85 °C −65 to 150 °C Note: Exceeding any of the absolute maximum ratings, even |
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Toshiba Semiconductor |
2 INPUT OR GATE avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorpor |
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Toshiba Semiconductor |
24-Stage Frequency Divider |
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Toshiba Semiconductor |
QUAD 2-INPUT NAND SCHMITT TRIGGERS ltage Output voltage DC input current Power dissipation Operating temperature range Storage temperature range VDD VIN VOUT IIN PD Topr Tstg VSS − 0.5 to VSS + 20 V VSS − 0.5 to VDD + 0.5 V VSS − 0.5 to VDD + 0.5 V ±10 mA 300 (DIP)/180 (SOIC |
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Toshiba Semiconductor |
8-Bit Addressable Latch |
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Toshiba Semiconductor |
(TC40xxxx) HEX BUFFER/CONVERTER 54A SOP16-P-300-1.27A SOL16-P-150-1.27 : 1.00 g (typ.) : 0.18 g (typ.) : 0.13 g (typ.) 1 2007-10-01 Pin Assignment TC4049B TC4049,4050BP/BF/BFN TC4050B Circuit Diagram 1/6 TC4049B 1/6 TC4050B Absolute Maximum Ratings (Note) Characteristics Sy |
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Toshiba Semiconductor |
QUAD EXCLUSIVE-OR GATE erature range VDD VIN VOUT IIN PD Topr Tstg VSS − 0.5 to VSS + 20 V VSS − 0.5 to VDD + 0.5 V VSS − 0.5 to VDD + 0.5 V ±10 mA 300 (DIP)/180 (SOIC) mW −40 to 85 °C −65 to 150 °C Note: Exceeding any of the absolute maximum ratings, even |
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Toshiba Semiconductor |
DUAL PRECISION RETRIGGERABLE/RESETTABLE MONOSTABLE MULTIVIBRATOR • twOUT = 10 ms ± 5% (at RX = 100 kΩ CX = 0.1 μF, VDD = 10 V) Pin Assignment TC4538BP TC4538BF Weight DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Truth Table (Note) Inputs A B CD HH LH HH LH **L Outputs QQ LH LH LH Note |
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Toshiba Semiconductor |
C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC |
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Toshiba Semiconductor |
QUAD 2-INPUT NAND SCHMITT TRIGGERS nsfer Characteristics Absolute Maximum Ratings (Note) Characteristics DC supply voltage Input voltage Output voltage DC input current Power dissipation Operating temperature range Storage temperature range Symbol VDD VIN VOUT IIN PD Topr Tstg Rating |
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Toshiba Semiconductor |
8-Bit Addressable Latch |
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Toshiba Semiconductor |
QUAD EXCLUSIVE-OR GATE wer dissipation Operating temperature range Storage temperature range VDD VIN VOUT IIN PD Topr Tstg VSS − 0.5 to VSS + 20 VSS − 0.5 to VDD + 0.5 VSS − 0.5 to VDD + 0.5 ±10 300 (DIP)/180 (SOIC) −40 to 85 −65 to 150 V V V mA mW °C °C Note: Exceedi |
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Toshiba Semiconductor |
QUAD BILATERAL SWITCH |
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Toshiba Semiconductor |
QUAD BILATERAL SWITCH BFN TC4066BFT Weight DIP14-P-300-2.54 SOP14-P-300-1.27A SOL14-P-150-1.27 TSSOP14-P-0044-0.65A : 0.96 g (typ.) : 0.18 g (typ.) : 0.12 g (typ.) : 0.06 g (typ.) 1 2007-10-01 Logic Diagram TC4066BP/BF/BFN/BFT 1/4 TC4066B I/O O/I CONT Absolute M |
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Toshiba Semiconductor |
CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC |
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Toshiba Semiconductor |
C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC |
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Toshiba Semiconductor |
QUAD 2-INPUT NAND SCHMITT TRIGGERS ltage Output voltage DC input current Power dissipation Operating temperature range Storage temperature range VDD VIN VOUT IIN PD Topr Tstg VSS − 0.5 to VSS + 20 V VSS − 0.5 to VDD + 0.5 V VSS − 0.5 to VDD + 0.5 V ±10 mA 300 (DIP)/180 (SOIC |
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Toshiba Semiconductor |
EXCLUSIVE-OR GATE |
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