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Silicon Laboratories 805 DataSheet

No. Partie # Fabricant Description Fiche Technique
1
C8051F526A

Silicon Laboratories
8/4/2 kB ISP Flash MCU
Datasheet
2
Si8055

Silicon Laboratories
1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS

 High-speed operation
 Default high or low output
DC to 10 Mbps
 Precise timing (typical)
 No start-up initialization required
40 ns propagation delay
 Wide Operating Supply Voltage
20 ns pulse width distortion
3.15
  – 5.5 V
10
Datasheet
3
C8051F520A

Silicon Laboratories
8/4/2 kB ISP Flash MCU
Datasheet
4
C8051F226

Silicon Laboratories
8K ISP FLASH MCU
ator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly Typical operating current: 9 mA at 25 MHz Typical stop mode current: <0.1 uA Memory Two comparators Digital Peripherals VDD Monitor and Brown-out Detector www.DataSheet4U
Datasheet
5
Si8050

Silicon Laboratories
1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS

 High-speed operation
 Default high or low output
DC to 10 Mbps
 Precise timing (typical)
 No start-up initialization required
40 ns propagation delay
 Wide Operating Supply Voltage
20 ns pulse width distortion
3.15
  – 5.5 V
10
Datasheet
6
C8051F564

Silicon Laboratories
Mixed Signal ISP Flash MCU
Datasheet
7
C8051F565

Silicon Laboratories
Mixed Signal ISP Flash MCU
Datasheet
8
C8051F340

Silicon Laboratories
Full Speed USB Flash MCU
rmance to emulation systems using ICE-chips, target pods, and sockets Voltage Supply Input: 2.7 to 5.25 V - Voltages from 3.6 to 5.25 V supported using On-Chip Voltage Regulator HIgh Speed 8051 μC Core - Pipelined instruction architecture; executes
Datasheet
9
C8051F019

Silicon Laboratories
Mixed-Signal 16KB ISP FLASH MCU
or: 2
  –16 MHz External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly Typical operating current: 12.5 mA at 25 MHz Multiple power saving sleep and shutdown modes Memory Two Comparators Internal Voltage Reference VD
Datasheet
10
C8051F045

Silicon Laboratories
8K ISP FLASH MCU
.................................................................................. 26 1.2. On-Chip Memory............................................................................................... 27 1.3. JTAG Debug and Boundary Scan.............
Datasheet
11
C8051F506

Silicon Laboratories
Mixed Signal ISP Flash MCU
Datasheet
12
C8051F507

Silicon Laboratories
Mixed Signal ISP Flash MCU
Datasheet
13
C8051F500

Silicon Laboratories
Mixed Signal ISP Flash MCU
Datasheet
14
C8051F503

Silicon Laboratories
Mixed Signal ISP Flash MCU
Datasheet
15
C8051T632

Silicon Laboratories
Mixed-Signal Byte-Programmable EPROM MCU
Datasheet
16
C8051F582

Silicon Laboratories
Mixed Signal ISP Flash MCU
0 to +125 °C C8051F58x/F59x Mixed Signal ISP Flash MCU Family Memory - 8448 bytes internal data RAM (256 + 8192 XRAM) - 128 or 96 kB Banked Flash; In-system programma- ble in 512-byte Sectors - External 64 kB data memory interface programma- ble for
Datasheet
17
C8051F017

Silicon Laboratories
Mixed-Signal 32KB ISP FLASH MCU
Chips, Target Pods, and Sockets - IEEE1149.1 Compliant Boundary Scan - Low Cost Development Kit HIGH SPEED 8051 C CORE - Pipelined Instruction Architecture; Executes 70% of Instruction Set in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25M
Datasheet
18
C8051F016

Silicon Laboratories
Mixed-Signal 32KB ISP FLASH MCU
Chips, Target Pods, and Sockets - IEEE1149.1 Compliant Boundary Scan - Low Cost Development Kit HIGH SPEED 8051 C CORE - Pipelined Instruction Architecture; Executes 70% of Instruction Set in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25M
Datasheet
19
C8051F000

Silicon Laboratories
Mixed-Signal 32KB ISP FLASH MCU
Chips, Target Pods, and Sockets - IEEE1149.1 Compliant Boundary Scan - Low Cost Development Kit HIGH SPEED 8051 C CORE - Pipelined Instruction Architecture; Executes 70% of Instruction Set in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25M
Datasheet
20
C8051F007

Silicon Laboratories
Mixed-Signal 32KB ISP FLASH MCU
Chips, Target Pods, and Sockets - IEEE1149.1 Compliant Boundary Scan - Low Cost Development Kit HIGH SPEED 8051 C CORE - Pipelined Instruction Architecture; Executes 70% of Instruction Set in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25M
Datasheet



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