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Semtech Corporation |
6-Bit D Register MC10E/100E151 Specified Over Industrial Temperature Range: –40oC to +85oC Available in 28-Pin PLCC Package PIN Description .unctional Block Diagram Pin D0D5 CLK1, CLK2 D0 D R Q0 Q0* .unction Data Inputs Clock Inputs Master Reset True Outputs Inve |
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Semtech Corporation |
1:9 Differential Clock Driver s, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being |
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Semtech Corporation |
Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator • • • • • • • • • • • • Extended Supply Voltage Range (VCC = +3.0V to 5.5V) 2.4 ns Typical Propagation Delay Differential PECL Inputs True Complementary CMOS/TTL Output Flow Through Pinouts Functionally compatible with MC10/100ELT21 and MC10/100LVELT |
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Semtech Corporation |
6-Bit D Register MC10E/100E151 Specified Over Industrial Temperature Range: –40oC to +85oC Available in 28-Pin PLCC Package PIN Description .unctional Block Diagram Pin D0D5 CLK1, CLK2 D0 D R Q0 Q0* .unction Data Inputs Clock Inputs Master Reset True Outputs Inve |
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Semtech Corporation |
1:2 Differential Fanout Buffer .unctional Block Diagram PIN Names Pin D, D* .unction Differential data Inputs Differential data Outputs Q0 1 8 VCC Q0, Q0*, Q1, Q1* Q0* 2 7 D Q1 3 6 D* Q1* 4 5 VEE Revision 1/February 12, 2001 1 www.semtech.com SK10/100EL11W H |
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Semtech Corporation |
Differential Receiver of input/output terminations. The different options of input/output terminations of the EL16TA-TD make them ideal for use in high frequency design applications. It can also reduce the part count where board space is scarce. The SK10/100EL16TA has a 1 |
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Semtech Corporation |
1:9 Signal Distribution hing to ECL Open Emitter l l l l l l Output Configuration 50Ω Double Termination 50Ω Source Termination Now Now Now Now Now Now Availability Open Collector Logic .amily Output Configuration Product SK1999 Open Collector l 12mA Q2 2001 Output Current |
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Semtech Corporation |
Quint Differential Line Receiver clamp circuitry to cause a defined output state if both the inverting and non-inverting inputs are left open; in this case the Q output goes low, while the Q* output goes high. This feature makes the device ideal for twisted pair applications. If bot |
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Semtech Corporation |
4-Bit D Flip-Flop • • • • • • • • 1100 MHz Minimum Toggle Frequency Differential Outputs Individual and Common Clocks Individual Resets (asynchronous) Paired Sets (asynchronous) Extended 100E VEE Range of –4.2V to –5.5V 75KΩ Internal Input Pulldown Resistors Fully Com |
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Semtech Corporation |
9-Bit Shift Register ous Master Reset Dual Clocks Extended 100E VEE Range of –4.2 to –5.5V 75KΩ Internal Input Pulldown Resistors Fully Compatible with MC10E142 and MC100E142 Specified over Industrial Temperature Range: –40oC to 85oC ESD Protection of >4000V Available in |
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Semtech Corporation |
4-Bit Serial/Parallel Converter multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 1 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmissi |
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Semtech Corporation |
4-Input OR / NOR Pin SOIC Package END VIEW TOP VIEW A D C 8 5 H E 1 4 B e 0.25 M B M h x 45o q A C A1 B 0.25 M C B S A S Seating Plane 0.10 L MILLIMETERS DIM A A1 B C D E e H h L θ MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 1. |
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Semtech Corporation |
2-Input XOR / XNOR Package PIN Descriptions END VIEW TOP VIEW A D C 8 5 H E 1 4 B e 0.25 M B M h x 45o q A C A1 B 0.25 M C B S A S Seating Plane 0.10 L MILLIMETERS DIM A A1 B C D E e H h L θ MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4 |
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Semtech Corporation |
1:2 Differential Fanout Buffer .unctional Block Diagram PIN Names Pin D, D* .unction Differential data Inputs Differential data Outputs Q0 1 8 VCC Q0, Q0*, Q1, Q1* Q0* 2 7 D Q1 3 6 D* Q1* 4 5 VEE Revision 1/February 12, 2001 1 www.semtech.com SK10/100EL11W H |
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Semtech Corporation |
Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver • • • • • • • • 100 ps Part-to-Part Skew 35 ps Output-to-Output Skew Differential Design VBB Output Low Voltage VEE Range of –2.375 to –3.8V for ECL Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL 75 KΩ Input Pulldown Resistors ECL/PECL Ou |
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Semtech Corporation |
8-Bit Synchronous Binary Up Counter internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to |
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Semtech Corporation |
8-Bit Synchronous Binary Up Counter internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to |
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Semtech Corporation |
8-Bit Synchronous Binary Up Counter internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to |
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Semtech Corporation |
1:9 Differential Clock Driver s, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being |
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Semtech Corporation |
Quint Differential Line Receiver clamp circuitry to cause a defined output state if both the inverting and non-inverting inputs are left open; in this case the Q output goes low, while the Q* output goes high. This feature makes the device ideal for twisted pair applications. If bot |
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