No. | Partie # | Fabricant | Description | Fiche Technique |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM® 32-bit Cortex®-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SR |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of |
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STMicroelectronics |
ARM-based 32-bit MCU Includes ST state-of-the-art patented technology • Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 6 |
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STMicroelectronics |
Arm-based Cortex-M4 32b MCU+FPU • Core: Arm® Cortex®-M4 32-bit CPU with FPU (72 MHz max), single-cycle multiplication and HW division, 90 DMIPS (from CCM), DSP instruction and MPU (memory protection unit) • Operating conditions: – VDD, VDDA voltage range: 2.0 V to 3.6 V • Memories |
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STMicroelectronics |
Low series inductance and resistance Schottky diodes ■ ■ ■ ■ ■ ■ BAS70ZFILM (Single) SOD-123 BAS70JFILM (Single) SOD-323 BAS70KFILM (Single) SOD-523 BAS70FILM (Single) BAS70-04FILM (Series) BAS70-05FILM (Common cathode) BAS70-06FILM (Common anode) Very low conduction losses Negligible switching losse |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of |
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STMicroelectronics |
ARM-based 32-bit MCU Includes ST state-of-the-art patented technology • Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 6 |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of |
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STMicroelectronics |
XL-density performance line ARM-based 32-bit MCU • Core: ARM® 32-bit Cortex®-M3 CPU with MPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 768 Kbytes to 1 Mbyte of Flash memory – |
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STMicroelectronics |
ARM-based 32-bit MCU • Core: Arm® 32-bit Cortex®-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 256 to 512 Kbytes of Flash memory – up to 64 Kbyt |
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STMicroelectronics |
XL-density performance line ARM-based 32-bit MCU ■ Core: ARM 32-bit Cortex™-M3 CPU with MPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ■ Memories – 768 Kbytes to 1 Mbyte of Flash memory – 9 |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of |
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STMicroelectronics |
advanced ARM-based 32-bit MCU • Core: ARM® 32-bit Cortex®-M3 CPU – 24 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance – Single-cycle multiplication and hardware division • Memories – 16 to 128 Kbytes of Flash memory – 4 to 8 Kbytes of SRAM • Clock, reset and sup |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM® 32-bit Cortex®-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SR |
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