| No. | Partie # | Fabricant | Description | Fiche Technique |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM® 32-bit Cortex®-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SR |
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STMicroelectronics |
Arm 32-bit Cortex-M4 CPU • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instr |
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STMicroelectronics |
ARM Cortex-M4 32-bit MCU+FPU • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memorie |
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STMicroelectronics |
32-bit MCU+FPU • Core: ARM® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1 cache: 4KB data cache and 4KB instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
Arm 32-bit Cortex-M4 CPU • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instr |
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STMicroelectronics |
32b MCU+FPU • Core: ARM® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1-cache: 4KB data cache and 4KB instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of |
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STMicroelectronics |
ARM-based 32-bit MCU Includes ST state-of-the-art patented technology • Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 6 |
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STMicroelectronics |
Arm-based Cortex-M4 32b MCU+FPU • Core: Arm® Cortex®-M4 32-bit CPU with FPU (72 MHz max), single-cycle multiplication and HW division, 90 DMIPS (from CCM), DSP instruction and MPU (memory protection unit) • Operating conditions: – VDD, VDDA voltage range: 2.0 V to 3.6 V • Memories |
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STMicroelectronics |
32-bit MCU • Core: Arm® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz • Memories – 16 to 256 Kbytes of Flash memory – 4 to 32 Kbytes of SRAM with HW parity • CRC calculation unit • Reset and power management – Digital & I/Os supply: VDD = 2.4 V to 3.6 V – Analo |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of |
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STMicroelectronics |
ARM-based 32-bit MCU Includes ST state-of-the-art patented technology • Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 6 |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 to 256 Kbytes of Flash memory – 64 Kbytes |
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STMicroelectronics |
ARM-based 32-bit MCU • ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of |
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STMicroelectronics |
XL-density performance line ARM-based 32-bit MCU • Core: ARM® 32-bit Cortex®-M3 CPU with MPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 768 Kbytes to 1 Mbyte of Flash memory – |
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