No. | Partie # | Fabricant | Description | Fiche Technique |
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Samsung semiconductor |
256MB DDR SDRAM MODULE The Samsung M368L3313DTL is 32M bit x 64 Double Data Rate SDRAM high density memory module. The Samsung M368L3313DTL consists of sixteen CMOS 16M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass- |
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Samsung Semiconductor |
SDRAM DIMM • Performance range Part No. M366S0823DTF-C10 • • • • • Max Freq. (Speed) 66MHz (@ CL=2 & CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles / 64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle wi |
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Samsung |
SDRAM Unbuffered Module |
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Samsung |
SDRAM Unbuffered Module |
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Samsung semiconductor |
256MB DDR SDRAM MODULE • Performance range Part No. Max Freq. Interface SSTL_2 M368L3223DTL-C(L)B3 167MHz(6.0ns@CL=2.5) M368L3223DTL-C(L)A2 133MHz(7.5ns@CL=2) M368L3223DTL-C(L)B0 133MHz(7.5ns@CL=2.5) • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate |
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Samsung |
256MB DDR SDRAM MODULE • Performance range Part No. Max Freq. Interface SSTL_2 M368L3223DTL-C(L)B3 167MHz(6.0ns@CL=2.5) M368L3223DTL-C(L)A2 133MHz(7.5ns@CL=2) M368L3223DTL-C(L)B0 133MHz(7.5ns@CL=2.5) • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate |
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Samsung |
DDR SDRAM Unbuffered Module • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • P |
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Samsung |
DDR SDRAM Unbuffered Module • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • P |
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Samsung |
DDR SDRAM Unbuffered Module • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • P |
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Samsung |
PC100 SDRAM MODULE |
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Samsung |
PC66 Unbuffered DIMM • Performance range Part No. KMM366S1623DTL-G0 • • • • • Max Freq. (Speed) 100MHz (10ns @ CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with |
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Samsung semiconductor |
PC133 Unbuffered DIMM • Performance range Part No. M366S3323CT0-C75 • • • • • Max Freq. (Speed) PC133@CL3 & PC100@CL3 Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with |
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Samsung Semiconductor |
DRAM Module • Part Identification Part number KMM366F804CS1 KMM366F884CS1 PKG TSOP TSOP Ref. 4K 8K CBR Ref. ROR Ref. 4K/64ms 4K/64ms 8K/64ms • New JEDEC standard proposal without buffer • Serial Presence Detect with EEPROM • Extended Data Out Mode Operation • |
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Samsung Semiconductor |
(KMM366F400CK/410CK) DRAM Module • Part Identification - KMM366F400CK (4096 cycles/64ms Ref. SOJ) - KMM366F410CK (2048 cycles/32ms Ref. SOJ) • New JEDEC standard proposal without buffer • Serial Presence Detect with EEPROM • Extended Data Out Mode Operation • CAS-before-RAS Refresh |
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Samsung Semiconductor |
(KMM366F883(8)CK2) DRAM Module • Part Identification Part number KMM366F803CK2 KMM366F883CK2 PKG SOJ SOJ Ref. 4K 8K CBR ref. ROR ref. 4K/64ms 4K/64ms 8K/64ms • New JEDEC standard proposal without buffer • Serial Presence Detect with EEPROM • Extended Data Out Mode Operation • CA |
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Samsung semiconductor |
(M368LxxxxBxM) DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die ......................................................................................................................................... 4 4.0 Pin Configuration (Front side/back side) ................................................................. |
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SAMSUNG |
(M368LxxxxCUx) DDR SDRAM Unbuffered Module • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) • Differential clock |
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Samsung Semiconductor |
Unbuffered DIMM • Performance range Part No. KMM366S823DTF-G0 • • • • • Max Freq. (Speed) 100MHz (10ns @ CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles / 64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle wit |
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Samsung Semiconductor |
SDRAM DIMM et4U.com et4U.com DataSheet4U.com DataShee DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com et4U.com DataSheet4U.com DataShee DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com et4U.com DataShee |
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Samsung Semiconductor |
Unbuffered DIMM • Performance range Part No. Max Freq. (Speed) KMM366S823CTS-G8 125MHz (8ns @ CL=3) KMM366S823CTS-GH 100MHz (10ns @ CL=2) KMM366S823CTS-GL 100MHz (10ns @ CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible in |
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