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PCIe Gen1-5 Low-Power PhiClock Generators ▪ 2 or 4 programmable output pairs plus 2 LVCMOS REF outputs ▪ 1MHz –325MHz LVDS or LP-HCSL outputs ▪ 1MHz-200MHz LVCMOS outputs Features ▪ 1.8V to 3.3V power supplies ▪ Individual 1.8V, 2.5V or 3.3V VDDO for each output pair ▪ Supports HCSL, LVDS an |
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Programmable PhiClock Generators ▪ 9FGV1001: 4 programmable output pairs plus 2 REF outputs ▪ 9FGV1005: 2 programmable output pairs plus 1 REF output ▪ 1 integer output frequency per configuration ▪ 1MHz –325MHz differential outputs ▪ 1MHz –200MHz single-ended outputs Features ▪ 1.8V |
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3.3V PCIe Gen1-5 Clock Generator ▪ 2, 4, 6, or 8 100MHz PCIe output pairs ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ 90fs RMS typical jitter (PCIe Gen5 CC) ▪ < 50ps cycle-to-cycle jitter |
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Frequency Gearing Clock Benefits • Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs) • Power up default is all outputs in 1:1 mode • DIF_(9:0) can be “gear-shifted” from the input CPU Host Clock • DIF_(11:10) can be “gear-shifted” from the input CPU Host Clock • Spread sp |
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PCIe Gen1-5 Low-Power PhiClock Generators ▪ 2 or 4 programmable output pairs plus 2 LVCMOS REF outputs ▪ 1MHz –325MHz LVDS or LP-HCSL outputs ▪ 1MHz-200MHz LVCMOS outputs Features ▪ 1.8V to 3.3V power supplies ▪ Individual 1.8V, 2.5V or 3.3V VDDO for each output pair ▪ Supports HCSL, LVDS an |
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4-OUTPUT VERY LOW POWER PCIE GEN 1-4 CLOCK GENERATOR • 4 0.7V low-power HCSL-compatible (LP-HCSL) DIF pairs with Zo=100 • 1 1.8V LVCMOS REF output with Wake-On-Lan (WOL) support Key Specifications • DIF cycle-to-cycle jitter < 50ps • DIF output-to-output skew < 50ps • DIF phase jitter is PCIe Gen1 –4 c |
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6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator • 6 100MHz Low-Power (LP) HCSL DIF pairs • 1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3-4 compliant • REF phase jitter |
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Low-Power Programmable PhiClock Generator ▪ 1 integer output frequency per configuration ▪ 2 programmable output pairs plus 1 LVCMOS REF output ▪ 1MHz –325MHz LVDS or LP-HCSL outputs ▪ 1MHz –200MHz LVCMOS outputs Block Diagram Features ▪ 1.8V –3.3V operation ▪ Individual 1.8V –3.3V VDDO for eac |
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3.3V PCIe Gen1-5 Clock Generator ▪ 2, 4, 6, or 8 100MHz PCIe output pairs ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ 90fs RMS typical jitter (PCIe Gen5 CC) ▪ < 50ps cycle-to-cycle jitter |
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Very Low-Power PCIe Gen1-4 Clock Generator ▪ Eight 100MHz Low-Power HCSL (LP-HCSL) DIF pairs with Zo = 100Ω ▪ One 1.8V LVCMOS REF output with Wake-On-LAN (WOL) support Key Specifications ▪ DIF cycle-to-cycle jitter < 50ps ▪ DIF output-to-output skew < 50ps ▪ DIF phase jitter is PCIe Gen1 –4 co |
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VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR • Two 0.7V low-power HCSL-compatible (LP-HCSL) DIF pairs with Zo = 100 • One 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support Key Specifications • DIF cycle-to-cycle jitter < 50ps • DIF output-to-output skew < 50ps • DIF phase jitter is PCIe Gen1 – |
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Programmable PhiClock Generators ▪ 9FGV1001: 4 programmable output pairs plus 2 REF outputs ▪ 9FGV1005: 2 programmable output pairs plus 1 REF output ▪ 1 integer output frequency per configuration ▪ 1MHz –325MHz differential outputs ▪ 1MHz –200MHz single-ended outputs Features ▪ 1.8V |
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8 OUTPUT LOW-POWER PCIE GEN1-2-3 CLOCK GENERATOR OCK GENERATOR W/ZO=100OHMS 5 9FGL839 REV B 072114 9FGL839 8 OUTPUT LOW-POWER PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS V/ns % 35 14 5.3 0.001 IDT® 8 OUTPUT LOW-POWER PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 6 9FGL839 REV B 072114 9FGL839 |
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120-MHz 32-bit RX MCU Datasheet RX65N Group, RX651 Group Renesas MCUs R01DS0276EJ0230 Rev.2.30 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory Jun 20, 2019 (supportive of the dual bank function), 640-KB SRAM, various communications interfaces |
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120-MHz 32-bit RX MCU Datasheet RX65N Group, RX651 Group Renesas MCUs R01DS0276EJ0230 Rev.2.30 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory Jun 20, 2019 (supportive of the dual bank function), 640-KB SRAM, various communications interfaces |
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120-MHz 32-bit RX MCU Datasheet RX65N Group, RX651 Group Renesas MCUs R01DS0276EJ0230 Rev.2.30 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory Jun 20, 2019 (supportive of the dual bank function), 640-KB SRAM, various communications interfaces |
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120-MHz 32-bit RX MCU Datasheet RX65N Group, RX651 Group Renesas MCUs R01DS0276EJ0230 Rev.2.30 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory Jun 20, 2019 (supportive of the dual bank function), 640-KB SRAM, various communications interfaces |
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FREQUENCY TIMING GENERATOR • 1 - 0.7V current-mode differential CPU pair • 8 - 50MHz output • 1 - DOT 96MHz output • 1 - 33.33MHz output • 1 - 32.768KHz output • 2 - 25MHz REF outputs Block Diagram Features/Benefits • Selectable SMBus Address – D0/D1 or C0/C1 • Spread Spectru |
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3.3V PCIe Gen1-5 Clock Generator ▪ 2, 4, 6, or 8 100MHz PCIe output pairs ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ 90fs RMS typical jitter (PCIe Gen5 CC) ▪ < 50ps cycle-to-cycle jitter |
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3.3V PCIe Gen1-5 Clock Generator ▪ 2, 4, 6, or 8 100MHz PCIe output pairs ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ 90fs RMS typical jitter (PCIe Gen5 CC) ▪ < 50ps cycle-to-cycle jitter |
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