Renesas 894 fiche technique

No.	Partie #	Fabricant	Description
1	ICS1894-40	Renesas	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER The ICS1894-40 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802.3. It is intended for RMII/MII, Node/Repeater a
2	ICS1894-32	Renesas	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER The ICS1894-32 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802.3. It is intended for RMII/MII Node application
3	ICS1894-44	Renesas	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX IEEE 8802.3 compliant • MII
4	ICS1894-34	Renesas	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant •
5	894D115I-04	Renesas	Clock/Data Recovery • Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3) • Input: NRZ data (622.08 or 155.52 Mbit/s) • Output: clock signal (622.08MHz or 155.52MHz) and retimed data signal at 622.08 or 155.52 Mbit/s • Internal PLL for clock generation and cl
6	ICS1894-43	Renesas	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX IEEE 8802.3 compliant • MII
7	ICS1894-34	Renesas	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant •
8	894D115I-01	Renesas	Clock/Data Recovery • Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3) • Input: NRZ data (622.08 or 155.52 Mbit/s) • Output: clock signal (622.08MHz or 155.52MHz) and retimed data signal at 622.08 or 155.52 Mbit/s • Internal PLL for clock generation and cl
9	2SC5894	Renesas Technology	Silicon NPN Transistor • High gain bandwidth product fT = 20 GHz typ. • High power gain and low noise figure; PG = 17.5 dB typ., NF = 1.8 dB typ. at f = 1.8 GHz Outline CMPAK-4 2 3 1 4 1. Emitter 2. Collector 3. Emitter 4. Base Note: Marking is “WJ –“. 2SC5894 Absolute
10	ISL89410	Renesas	Dual Channel Power MOSFET Drivers
11	ISL89411	Renesas	Dual Channel Power MOSFET Drivers
12	ISL89412	Renesas	Dual Channel Power MOSFET Drivers
13	ISL89400	Renesas	High Frequency Half-Bridge Drivers • Drives N-channel M
14	ISL89401	Renesas	High Frequency Half-Bridge Drivers • Drives N-channel M