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Philips |
Car Radio Digital Signal Processor adapted • RDS description adapted N1B final version • Fig. 8.15 : changed. Resistor R16/R18 is added • Fig. 8.23 : changed. Resistor R5 is added • Table 8.2 : Timing (unit) RDS changed • Chapter 8.8 : Chapter “Interface with tuner TEA6840 is added P |
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Philips |
Stereo CMOS DAC • 2 1 S data input • 3-stage digital filter incorporating F.I.R. filter, linear interpolator and sample and hold • 2nd order noise shaper to provide a signal-to-noise ratio of> 90 dB • 16-bit resolution from a 1-bit converter, using switched |
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Philips |
(SAA4848 / SAA4849) digital deflection controller are added: • Integrated soft start mechanism of the B+ voltage controller during startup and during mode changing ensuring safe operation of the various deflections transistors and diodes. • Integrated I2C -bus controller B+ voltage adjustment • Unde |
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Philips |
Radio tuning PLL frequency synthesizer • On-chip prescaler with up to 120 MHz input frequency. • On-chip AM and FM input amplifiers with high sensitivity (30 mV and 10 mV respectively). • Low current drain (typically 16 mA for AM and 20 mA for FM) over a wide supply voltage range (3,6 V t |
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Philips |
TV microcontrollers 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION 6.1 Pinning 6.2 Pin description 7 MICROCONTROLLER 7.1 Microcontroller features 8 MEMORY ORGANIZATION 8.1 ROM bank switching 8.2 RAM organisation |
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Philips |
125MHz Amplifier and Divider-BY-32/33 N 125 MHz amplifier and divider-by-32/33 SAA1059 no' n .1 .2.3 .16 .17 .18 .31 .32 .33 IN H ~---~---~ -+J ---r---j , -------~--~ -----t----- i ~_._~ 7Z80062.A '5 SEINT QaEECCLL orCQaMoOc3C3 HL H LL n-l n .1 H ~. H --41 .2.3 * .16.17 . |
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Philips |
Car Radio Digital Signal Processor adapted • RDS description adapted N1B final version • Fig. 8.15 : changed. Resistor R16/R18 is added • Fig. 8.23 : changed. Resistor R5 is added • Table 8.2 : Timing (unit) RDS changed • Chapter 8.8 : Chapter “Interface with tuner TEA6840 is added P |
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Philips |
Memory controller • Support for acquisition, display and deflection PLL • 50/100 Hz (or 60/120 Hz) scan conversion • Progressive scan 50 Hz/1250 lines (60 Hz/1050 lines) interlaced or 50 Hz/625 lines (60 Hz/525 lines) non-interlaced in serial memory structure • 50 Hz/ |
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Philips |
Teletext video processor • Fixed horizontal compression by a factor of video standards • 5 MHz bandwidth • Bypass function • Inputs for luminance and chrominance of side panels • Standard video inputs and outputs (Y, (B−Y) and (R−Y)) • Horizontal and vertical sync signals ar |
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Philips |
Multistandard video decoder SAA7117 and SAA7117A SAA7117A SAA7117 Applications GENERAL DESCRIPTION ORDERING INFORMATION PINNING FUNCTIONAL DESCRIPTION Block diagram Analog Frontend of SAA7117A Analog Frontend of SAA7117 Video decoder (luminance and chrominance processing, Combf |
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Philips |
TV microcontrollers 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION 6.1 Pinning 6.2 Pin description 7 MICROCONTROLLER 7.1 Microcontroller features 8 MEMORY ORGANIZATION 8.1 ROM bank switching 8.2 RAM organisation |
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Philips |
Infrared remote control transmitter RECS 80 low voltage • Modulated transmission • Ceramic resonator controlled frequency • Data-word-start with reference time of unique start pattern • Supply voltage range 2 V to 6.5 V • 40 mA output current capability • Very low standby current (< 4 µA at VDD = 6 V) • U |
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Philips |
LIne MEmory noise Reduction IC LIMERIC • 2-D adaptive vertically recursive noise reduction • Noise reduction for Y, U and V signals in 4 : 1 : 1 format • Single 5 V ±10% power supply • Communication by means of serial communication protocol 83C654 (SNERT bus) • Via SNERT bus, 10 different |
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Philips |
PANorama-IC PAN-IC • Complete Teletext decoder in a 48-pin DIL or 64-pin QFP, integrated circuit • Single +5 V power supply • Both video and scan related synchronization modes are supported • RGB interface to standard colour decoder ICs, push-pull output drive • Digita |
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Philips |
Analog TV Video and Stereo Decoder to a variety of computing and consumer products. Analog TV video and stereo decoder for computing and consumer applications in North America and Japan Semiconductors On a single chip, the SAA7173 TV video/stereo decoder handles fully automatic det |
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Philips |
Multistandard video decoder SAA7117 and SAA7117A SAA7117A SAA7117 Applications GENERAL DESCRIPTION ORDERING INFORMATION PINNING FUNCTIONAL DESCRIPTION Block diagram Analog Frontend of SAA7117A Analog Frontend of SAA7117 Video decoder (luminance and chrominance processing, Combf |
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Philips |
Terrestrial Digital Sound Decoder |
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Philips |
Infrared remote control decoder • Decodes 64 remote control commands with a maximum of 32 subaddresses • Accepts RECS80 codes with pulse position modulation (SAA3004, SAA3007, SAA3008) or RC5 codes with bi-phase transmission (SAA3006, SAA3010) • Suitable for low voltage and low SAA |
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Philips |
Integrated PAL comb filter • One chip adaptive PAL comb filter • Time discrete but continuous amplitude signal processing with analog interfaces • Internal delay lines, filters, clock processing and signal switches • Alignment-free • No hanging dots or residual cross colour on |
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Philips |
Progressive scan-Zoom and Noise reduction IC • Adaptive data slicer • Crystal-controlled data clock regeneration with a bit rate of 6.9375 MHz • Adaptive sync separator, horizontal phase detector and 13.5 MHz VCO to provide display phase locked loop (PLL) • TV synchronization at teletext mode |
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