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Philips |
16-bit serial/parallel-in / serial-out shift register • 16-bit serial I/O shift register • 16-bit parallel-in/serial-out converter • Recirculating serial shifting • Common serial data I/O pin (3-State) DESCRIPTION The 74F674 is a 16-bit shift register with serial and parallel load capability and serial |
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Philips |
Octal transceiver/register • Combines 74F245 and two 74F374 type functions in one chip • High impedance base inputs for reduced loading (70µA in high and low states) DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits |
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Philips |
Up/down binary counter • Synchronous reversible 4-bit counting • Asynchronous parallel load capability • Asynchronous reset (clear) • Cascadable without external logic DESCRIPTION The 74F193 is a 4-bit synchronous up/down counter in the binary mode. Separate up/down clock |
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Philips |
Octal transparent latch 74F573/74F574 • 74F573 is broadside pinout version of 74F373 • 74F574 is broadside pinout version of 74F374 • Inputs and Outputs on opposite side of package allow easy interface to Microprocessors The 74F574 is functionally identical to the 74F374 |
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Philips |
Octal shift/count registered transceiver • High speed parallel registers with this device only on the output states. Both OE pins are enabled low. All operating modes, other than clear, 3 –State, and the two hold modes require the rising edge of the clock. All setup and hold times must be o |
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Philips |
Octal D flip-flop • 74F564 is broadside pinout version of 74F534 • Inputs and Outputs on opposite side of package allow easy interface to Microprocessors PIN CONFIGURATION OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 |
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Philips |
9-Bit address/data Futurebus transceiver • 9 –bit transceiver (both directions) • Drives heavily loaded backplanes with equivalent load impedances down to 10 ohms • High drive (100mA) open collector drivers on B port • Reduced voltage swing (1V to 2V) produces less noise and reduces power c |
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Philips |
Octal registered transceiver • 8-bit bidirectional I/O port with handshake • Register status flag flip-flops • Separate clock enable and output enable • Parity generation and parity check • B outputs and parity output sink 64mA DESCRIPTION The 74F522 Octal Registered Transceiver |
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Philips |
Up/down binary counter • High speed –125MHz typical fMAX • Synchronous, reversible counting • 4-Bit binary • Asynchronous parallel load capability • Cascadable without external logic • Single up/down control input DESCRIPTION The 74F191 is a 4-bit binary counter. It conta |
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Philips |
4-bit bidirectional universal shift register • Shift right and shift left capability • Synchronous parallel and serial data transfer • Easily expanded for both serial and parallel operation • Asynchronous Master Reset • Hold (do nothing) mode DESCRIPTION The functional characteristics of the 7 |
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Philips |
16 4 Synchronous FIFO outputs • Independent synchronous inputs and • Organized as 16 words of 4 bits • DC to 50MHz data rate • 3-State outputs • Cascadable in word –width and depth direction TYPICAL SUPPLY CURRENT (TOTAL) 90mA DESCRIPTION This 64-bit active element First |
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Philips |
Octal inverter buffer • Octal bus interface • 3-State buffer outputs sink 64mA • 15mA source current • Guaranteed output skew less than 2.0ns (74F240A/74F241A) • Reduced ground bounce (74F240A/74F241A) DESCRIPTION The 74F240 and 74F241 are octal buffers that are ideal f |
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Philips |
Quad 2-lnput selector/multiplexer • Industrial range available ( –40°C to +85°C) • Multifunction capability • Non-inverting data path • 3-State outputs • See 74F258A for inverting version DESCRIPTION The 74F257A has four identical 2-input multiplexers with 3-State outputs which selec |
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Philips |
9-bit odd/even parity generator/checker • High-impedance NPN base inputs for reduced loading (20µA in Low and High states) PIN CONFIGURATION I6 I7 NC I8 ΣE ΣO GND 1 2 3 4 5 6 7 14 VCC 13 I5 12 I4 11 I3 • Buffered inputs — one normalized load • Word length easily expanded by cascading • |
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Philips |
Octal registered transceiver 74F543, 74F544 Octal registered transceiver, non-inverting (3-State) Octal registered transceiver, inverting 93-State) FUNCTIONAL DESCRIPTION The 74F543 and 74F544 contain two sets of eight D-type latches, with separate input and controls for each |
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Philips |
Quad 2-to-1 data selector multiplexer for 74F723A/74F723-1 • Consists of four 3-to-1 Multiplexers • High impedance PNP base inputs for reduced loading (20µA in High and Low states) input • Inverting or non-inverting data path capability by an inverting (INV) • Designed for address mult |
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Philips |
Bus interface registers flip-flops • High speed parallel registers with positive edge-triggered D-type • High performance bus interface buffering for wide data/address paths or busses carrying parity • High impedance PNP base inputs for reduced loading (20µA in high and l |
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Philips |
64-bit TTL bipolar RAM • High speed performance • Replaces 74F219 • Address access time: 8ns max vs 28ns for 74F219 • Power dissipation: 4.3mW/bit typ • Schottky clamp TTL • One chip enable • Non –Inverting outputs (for inverting outputs see 74F189A) • 3 –state outputs • 74 |
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Philips |
Quad transceiver/inverting ALUE HIGH/LOW 70µA/1.0mA 70µA/1.6mA 20µA/1.0mA 20µA/1.0mA 15mA/64mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOLS 74F242 3 4 5 6 3 4 5 6 74F243 A0 A1 A2 A3 A0 A1 A2 A3 1 13 OEA |
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Philips |
8-input multiplexer • High speed 8-to-1 multiplexing • On chip decoding • Multifunction capability • Inverting and Non-Inverting outputs • Both outputs are 3-State for further multiplexer expansion DESCRIPTION The 74F251A is a logic implementation of a single 8-positio |
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