| No. | Partie # | Fabricant | Description | Fiche Technique |
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ON Semiconductor |
1.8V / 2.5V 10Gbps Equalizer Receiver • Maximum Input Data Rate > 10 Gbps • Maximum Input Clock Frequency > 7.5 GHz • Backplane and Cable Interconnect Compensation • 225 ps Typical Propagation Delay • 30 ps Typical Rise and Fall Times • Differential CML Outputs, 400 mV Peak-to-Peak, Typi |
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ON Semiconductor |
3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler |
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ON Semiconductor |
Clock Divider w/CML Output and Internal Termination • Maximum Input Clock Frequency 14 GHz Typical • 200 ps Max Propagation Delay • 30 ps Typical Rise and Fall Times • < 0.5 ps Maximum (RMS) Random Clock Jitter • Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V • CML Output Level (400 mV Peak− |
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ON Semiconductor |
12 Gb/s Differential Clock/Data SmartGate |
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ON Semiconductor |
a high performance differential 1:8 Clock/Data fanout buffer • Input Data Rate > 12 Gb/s Typical • Data Dependent Jitter < 20 ps • Maximum Input Clock Frequency > 8 GHz Typical • Random Clock Jitter < 0.8 ps RMS • Low Skew 1:8 CML Outputs, < 25 ps max • Multi−Level Inputs, accepts LVPECL, CML, LVDS • 160 ps Ty |
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ON Semiconductor |
2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator QFN−16 MN SUFFIX CASE 485G NB7L 11M ALYWG G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • Ma |
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ON Semiconductor |
Clock Divider • Maximum Input Clock Frequency > 10 GHz, typical • Random Clock Jitter < 0.8 ps RMS • 200 ps Typical Propagation Delay • 35 ps Typical Rise and Fall Times • Differential CML Outputs, 400 mV Peak−to−Peak, Typical • Operating Range: VCC = 1.71 V to 2. |
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ON Semiconductor |
1.8V / 2.5V /3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator • Input Data Rate > 10 Gb/s Typical • Data Dependent Jitter < 10 ps • Maximum Input Clock Frequency > 6 GHz Typical • Random Clock Jitter < 0.8 ps RMS • Low Skew 1:2 CML Outputs, < 15 ps max • 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML, LVDS • 1 |
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ON Semiconductor |
1.8V USB 3.1 Single Channel Re-driver an intelligent LFPS circuit. This circuit senses the low frequency signals and automatically disables driver de−emphasis for full USB 3.1 Gen 1 and USB 3.1 Gen 2 compliances. After power up, the NB7VPQ701M periodically checks both of the TX output pa |
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ON Semiconductor |
6.125Gb/s 1:10 Differential Clock/Data Driver http://onsemi.com 1 52 QFN−52 MN SUFFIX CASE 485M MARKING DIAGRAM* 52 1 NB7L 111M AWLYYWWG • • • • • • • • • • • • • Maximum Input Clock Frequency > 5.5 GHz Typical Maximum Input Data Rate > 6.125 Gb/s Typical < 0.5 ps Maximum Clock RMS Jitter |
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ON Semiconductor |
Differential 1:4 Clock/Data Fanout Buffer/Translator QFN−16 MN SUFFIX CASE 485G NB7L 14M ALYWG G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • • |
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ON Semiconductor |
High Gain Receiver/Buffer/Translator 16 1 QFN−16 MN SUFFIX CASE 485G NB7L 216 ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. V |
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ON Semiconductor |
Differential 2 x 2 Crosspoint Switch • Maximum Input Data Rate > 10 Gb/s • Data Dependent Jitter < 10 ps pk−pk • Maximum Input Clock Frequency > 7 GHz • Random Clock Jitter < 0.5 ps RMS, Max • 150 ps Typical Propagation Delay • 30 ps Typical Rise and Fall Times • Differential CML Output |
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ON Semiconductor |
1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator http://onsemi.com MARKING DIAGRAM* 1 1 32 QFN32 MN SUFFIX CASE 488AM NB7V 586M AWLYYWW G A WL YY WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND |
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ON Semiconductor |
1.8 V / 2.5 V / 3.3 V Differential 2:1 Clock / Data Multiplexer / Translator www.DataSheet4U.com 1 QFN−16 MN SUFFIX CASE 485G NB7V 58M ALYW G G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Applicatio |
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ON Semiconductor |
1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7V PQ16M ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. SDO |
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ON Semiconductor |
1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7V Q58M ALYW G G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. SI |
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ON Semiconductor |
2.5 V / 3.3 V Differential 4:1 Mux Input To 1:2 LVPECL Clock/Data Fanout/Translator |
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ON Semiconductor |
Differential 1:6 LVPECL Clock/Data distribution • Maximum Input Data Rate > 8 Gb/s • Data Dependent Jitter < 15 ps • Maximum Input Clock Frequency > 5 GHz • Random Clock Jitter < 0.8 ps RMS • Low Skew 1:6 LVPECL Outputs, 20 ps max • 2:1 Multi−Level Mux Inputs • 175 ps Typical Propagation Delay • 5 |
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ON Semiconductor |
Differential1-to-6 CML clock/data distribution SIMPLIFIED LOGIC DIAGRAM VCC Q0 Q0 SEL VREFAC0 IN0 VT0 IN0 0 Q1 Q1 Q2 Q2 IN1 VT1 IN1 VREFAC1 VCC GND 1 Q3 Q3 Q4 Q4 Q5 Q5 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this |
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